The influence of temperature and dielectric materials on stress induced voiding in Cu dual damascene interconnects

Abstract

In this work, package level stress migration test of Cu dual-damascene interconnects in via-line structures was performed. The effects of stressing temperature and dielectric materials on SIV behavior were investigated. The via-line structures were studied at temperatures ranging from 150 to 250 °C, with highest failure rate being detected at 200 °C. In comparing stress migration data on carbon doped oxide (CDO) with undoped silica glass (USG), a difference of two orders of magnitude was detected in the rate of change of resistance. About 40% of the CDO samples showed open circuit failures after a 1344-h test, whereas the maximum resistance change in the USG samples was only 10%. Failure analysis indicated that failures in both CDO and USG were very similar in nature. In both cases, voids formed symmetrically at the bottom of the via, showing that the integrity of the Ta barrier in the via bottom area was of significant influence to stress induced voiding. Finite element analysis (FEA) indicated that the driving force for void growth, the gradient of hydrostatic stress, at via bottom in CDO structure is 30% higher than the one in USG. Besides the stress gradient, other factors that could affect SIV behaviour are the back stress and interface adhesion. Similar to the case of electromigration, back stress might be generated during stress migration, provided that the interface between the Cu line and the surrounding dielectric material is strong. Back stress reverses the trend of migration of atoms. Discussion and comparison of all these factors are made between the two types of dielectrics in order to explain the observed higher failure rate of stress-induced-voiding in CDO structures.