VLSI System Design Research Articles

LOW POWER OPTIMIZATION OF FULL ADDER CIRCUIT BASED ON GDI LOGIC FOR BIOMEDICAL APPLICATIONS

Advanced Electronic Devices have recently become more prevalent, designers have opted for low power, quick speed, and compact designs and processes. Even though there are numerous design methodologies currently in use for VLSI system design optimization, very few design techniques produce solutions that are optimally optimal. GDI-based circuits are becoming increasingly important since they use less space, power, and energy. The GDI technique ensures minimal propagation delay, power, and area in low-power design strategies. For 45nm technology, the Cadence Virtuoso EDA tool is utilised to determine delay and power. The proposed designs examination of delay and power performance at 1.0V voltage produced positive findings. The Gate Diffusion Input concept serves as the foundation for the proposed design in this work. In order to achieve a full voltage swing of the output, a 1-bit full adder circuit design using GDI is demonstrated in this work. The GDI with the Full Swing Technique is presented in this work. Applying the suggested way to a 45nm complete adder from 14 Transistors. It is evident from the obtained simulation results that the suggested design uses the least power and the least amount of delay when compared to other full adder circuits that are already in use. Consequently, compared to previous full adder GDI circuit designs, the output voltage swing is in full and the overall power-delay product is improved by 60 percent.

Electrothermal Simulation and Optimal Design of Thermoelectric Cooler Using Analytical Approach

In this article, electrothermal modeling and simulation of thermoelectric cooling (TEC) in the package design of VLSI systems are performed by solving coupled heat conduction and current continuity equations. We propose a new analytical solution to the coupled partial differential equations (PDEs) which describe temperature and voltage with the reduction from 3-D to 1-D. In addition to this, we derive new analytic expressions for two key performance metrics for TEC devices: 1) the maximum temperature difference and 2) the maximum heat-flux pumping capability, which can be guided for the optimal design of thermoelectric cooler to achieve the maximum cooling performance. Furthermore, for the first time, we observe that when the dimensionless figure of merit <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$ZT_{0}$ </tex-math></inline-formula> value is larger than 1, there is no maximum heat-flux value, which means the heat dissipation due to the Peltier and Fourier transfer effects is larger than the heat generation caused by the Joule heating effect, which can lead to more efficient TEC cooling design. The accuracy of the proposed 1-D formulas is verified by a 3-D finite element method using COMSOL software. The compact model delivers many orders of magnitude speedup and memory saving compared to COMSOL with marginal accuracy loss. Compared with the conventional simplified 1-D energy equilibrium model, the proposed analytical coupled multiphysics model is more robust and accurate.

Investigation and Analysis of Power Performance Area (PPA) Cards of Digital Multiplier Architectures

The crucial role played by digital multipliers in VLSI system design makes it indispensable to study the PPA cards of digital multiplier architectures before tailoring multiplier architecture into such systems. Therefore, in this work, we present a detailed investigation and analysis of PPA cards of popular digital multiplier architectures, for various wordlengths. Each multiplier has been implemented on Artix-7 FPGA xc7a200tfbg676-2 and analyzed using Xilinx Vivado Design Suite 2019.2. A major contribution in this paper is the study of energy profiles of the architectures, not focused on in the earlier literature. This study compares their device utilization, timing parameters, power consumption, and energy profiles. Results indicate that Dadda Tree Multiplier and Wallace Tree Multiplier (460 slices and 557 slices, respectively, for [Formula: see text] bits) are undoubtedly the least slices consuming fast multipliers, but their power consumption and energy density are high as well. For 32-bit implementation, Vedic Multiplier consumes 48.9% lower power than Dadda Tree Multiplier, while the latter occupies 30.42% lesser slices. The speed of the Vedic Multiplier is in close proximity with the tree multipliers. The energy density of Vedic Multiplier (0.3[Formula: see text]nJ/slice) is much lower than that of Dadda Tree Multiplier (0.77[Formula: see text]nJ/slice).

Local Binary Patterns Based on Neighbor-Center Difference Image for Color Texture Classification with Machine Learning Techniques

This is a topic that receives a lot of interest since many applications of computer vision focus on the detection of objects in visually appealing environments. Information about an object’s appearance and information regarding the object’s motion are both used as crucial signals in the process of identifying and recognising any given item. This information is used to characterise and recognise the item. The identification of objects based solely on their outward appearance has been the subject of a substantial amount of research. However, motion information in the recognition task has received only a marginal amount of attention, despite the fact that motion plays an essential role in the process of recognition. In order to analyze a moving picture in a way that is both fast and accurate, it is required to make use of motion information in conjunction with surface appearance in a strategy that has been designed. Dynamic texture is a kind of visual phenomenon that may be characterised as a type of visual phenomenon that shows spatially repeated features as well as some stationary properties during the course of time by using methodologies that are associated with machine learning. The design of modern VLSI systems takes into consideration a larger chip density, which results in a processor architecture with several cores that are capable of performing a wide range of functions (multicore processor architecture). It is becoming more challenging to run such complicated systems without the use of electric power. In order to increase the effectiveness of power optimization strategies while maintaining system performance for text data extraction, it has been developed and put into practice power optimization strategies that are based on scheduling algorithms. Over the last twenty years, texture analysis has been an increasingly busy and profitable field of study. Today, texture interpretation plays a vital role in various activities ranging from remote sensing to medical picture analysis. The absence of tools to newline analyze the many properties of texture pictures was the primary challenge faced by the texture analysis approach. Texture analysis may be roughly categorised as texture classification, texture segmentation, texture synthesis, and texture synthesis. Texture categorization is useful in numerous applications, such as the retrieval of picture databases, industrial agriculture applications, and biomedical applications. Texture categorization relies on three distinct methods, namely, statistical, spectral, and structural methods. Statistical methods are based on the statistical characteristics of the image’s grey level. Features are collected using second order statistical order, autocorrelation function, and grey level co-occurrence matrix function.

Adaptive Counter Clock Gated S-Box Transformation Based AES Algorithm of Low Power Consumption and Dissipation in VLSI System Design

Advanced Encryption Standard (AES) is an effective algorithm trending today. According to the key length, it works efficiently. Here three types of key lengths are used such as 128, 192, and 256 bits. This paper introduced an Adaptive Counter-Clock (ACC) S-Box algorithm. This algorithm rectifies the error during data encryption and secure data from hackers. In this paper, we have done power consumption, power dissipation, and reduced the area size. Field Programmable Gate Array (FPGA) is utilized for hardware execution in the encryption process. Inverse Mix Column, Inverse Sub Bytes (S-Box) and Inverse Shift Row stages takes place in the decryption, so that the receiver can read the message in plain text which was sent by the sender. For this the receiver should have the same key used by the sender for encryption process. RTL coding is done using Verilog HDL, Xilinx ISE 14.7 FPGA will be used in the implementation.

Design of Low Power SRAM Cell Using Adiabatic Logic

In VLSI system design power consumption and energy dissipation are become more important. To optimize the power consumption we are using adiabatic logic which is having capability of reusing power. In this paper we proposed novel 7T SRAM cell using MCPL adiabatic logic. We compared the performance of energy dissipation and power consumption of conventional 7T SRAM and adiabatic SRAM. Furthermore, the conventional 6T,7T SRAM cell and the designs which are related are designed using FINFET devices to achieve low power.7T SRAM is more stable compared to 6T SRAM but due to excess transistor in 7T SRAM the power consumption will be more. SRAM cells are designed in cadence EDA environment and layouts for these circuits are carried out in cadence Assura tool.

Performance Analysis of Multipliers Using Modified Gate Diffused Input Technology

The primitive constraints in any VLSI system design are power, delay and area. Systems based on CMOS logic consume more power and area. Higher power dissipation will have a direct effect on the lifetime and performance of digital systems. Adders and multipliers form the core of almost all the digital systems like Microprocessor, Digital Signal Processors (DSPs), etc., so the adders and multipliers need to be optimized in terms of power, area and delay for an efficient and cost-effective processor design. This paper presents an approach for implementing 8-bit Array multiplier, Wallace Tree multiplier and Vedic multiplier using modified Gate Diffusion Input (m-GDI) technology and comparative analysis against area, power and delay. From the analysis, it is found that multipliers, which are built on m-GDI logic, occupy less area, dissipate less power and experience less delay than the multipliers based on CMOS logic, GDI logic and Booth multiplier. Also among the three m-GDI-based multipliers, Vedic multiplier performs better in terms of area, speed and power than array multiplier and Wallace tree multiplier.

RETRACTED ARTICLE: Low power area optimized and high speed carry select adder using optimized half sum and carry generation unit for FIR filter

In VLSI system design, one of the most significant areas of on-going research is high speed with low power system design. Usually the speed of the VLSI circuits like binary adders can be improved by more parallelism but, this more parallelism idea will increase the power consumption and area of the circuit. Therefore there is a trade-off between speed and power/area. A carry select adder is one of the fast binary adders but it consumes more power and area. In this paper, we proposed a low power and area efficient and high speed binary carry select adder (CSLA). The half sum and carry generator (HSCG) of the proposed CSLA is designed with a new methodology, that the HSCG output are estimated using input A and B not with carry-in hence it is faster and results in less area leads to low power consumption. Moreover, the NAND gate based circuit is used to compute the intermediate carries within the block and carry-out of the block which are derived from HSCG output along with carry-in. Similarly, the full sum of the proposed adder is generated from XNOR gate based circuitry by utilizing the intermediate carries of the block. The existing and proposed CSLAs are synthesized with the Synopsys EDA tool using 32 nm CMOS technology. The performance of the existing and proposed designs are analyzed and the results shows that the proposed 64-bit CSLA exhibits average reduction of 43% in power and average of 25% less utilization in terms of area compared to existing design. This proposed CSLA is used in a FIR Filter and obtained significant reduction in ADP and PDP.

Introduction to the Special Issue on the 2019 Symposium on VLSI Circuits

This Special Issue of the IEEE Journal of Solidstate Circuits highlights some of the best papers presented at the 33rd Symposium on VLSI Circuits, held on June 10–14, 2019, at Rihga Royal Hotel Kyoto, Kyoto, Japan. Industry and university engineers from all over the world reported innovative new techniques and state-of-the-art results. Articles presented covered a broad range of topics important to VLSI circuit and system designers, including topics also important to integrated circuit technology developers.

VERIFICATION OF CARRY LOOK AHEAD ADDER USING CONSTRAINED RANDOMIZED LAYERED TEST BENCH

In processors and in digital circuit designs, adder is an important component. As a result, adder is the main area of research in VLSI system design for improving the performance of a digital system. The performance depends on power consumption and delay. Adders are not only used for arithmetic operations, but also for calculating addresses and indices. In digital design we have half adder and full adder, by using these adders we can implement ripple carry adder (RCA). RCA is used to perform any number of additions. In this RCA is serial adder and it has propagation delay problem. With increase in hard &amp; fast circuits, delay also increases simultaneously. That’s the reason these Carry look ahead adders (CLA) are used. The carry look ahead adder speeds up the addition by reducing the amount of time required to determine carry bits. It uses two blocks, carry generator (Gi) and carry propagator (Pi) which finds the carry bit in advance for each bit position from the nearest LSB, if the carry is 1 then that position is going to propagate a carry to next adder.

Performance of Different Full Adder Structures for Optimized Design

Design of high performance and energy efficient digital systems are one of the most important research areas in VLSI system design which is suitable for real-time applications. One of the functional elements used in complex arithmetic circuits is an adder. To design an energy efficient adder one-bit full adder cell is designed based on adiabatic logic. The proposed ALFA cell is designed using adiabatic logic which results with the negligible amount of exchange of energy with the surrounding environment. Therefore, the application circuits based on this logic will have negligible energy loss due to heat dissipation. It requires 24 transistors to get the true and complimentary arithmetic sum and carry output. The proposed adiabatic logic based full adder (ALFA) cell processes the three single bit inputs and provides the output as sum, carry, sum bar and carry bar in a single architecture. The proposed ALFA cell reduces the power consumption by 98.49%, 90.93%, and 89.37%, respectively, when compared to CMOS full adder, 14T pass-transistor logic (PTL) with transmission gate (TG) full adder and 16T PTL with TG full adder.

Low Power High Speed Arithmetic Circuits

In the Design of arithmetic circuits reducing area, high speed and power are the major areas in VLSI system design. In this paper parallel prefix adders like Kogge-stone adder, Breunt-Kung adder, Ladner-Fischer adder is designed .Radix-4 Booth multiplier is designed by using Kogge-Stone adder. 16 bit Vedic multiplier is done by using Urdhwa Triyambaka sutra .8bit Vedic division is implemented by using Crumbs method so as to reduce the area, LUT tables and increase the speed as well as to reduce the Power dissipiation. The design is synthesized using Xilinx ISE 14.1 design suite.

VLSI implementation of ultra power optimized adiabatic logic based full adder cell

Design of high performance and energy efficient digital systems are one of the most important research areas in VLSI system design which is suitable for real-time applications. One of the functional elements used in complex arithmetic circuits is an adder. To design an energy efficient adder one-bit full adder cell is designed based on adiabatic logic. The proposed ALFA cell is designed using adiabatic logic which results with the negligible amount of exchange of energy with the surrounding environment. Therefore, the application circuits based on this logic will have negligible energy loss due to heat dissipation. It requires 24 transistors to get the true and complimentary arithmetic sum and carry output. The proposed adiabatic logic based full adder (ALFA) cell processes the three single bit inputs and provides the output as sum, carry, sum bar and carry bar in a single architecture. The proposed ALFA cell reduces the power consumption by 98.49%, 90.93%,and 89.37%, respectively, when compared to CMOS full adder, 14T pass-transistor logic (PTL) with transmission gate (TG) full adder and 16T PTL with TG full adder.

Introduction to the Special Issue on the 2018 Symposium on VLSI Circuits

This Special Issue of the IEEE Journal of Solid-State Circuits highlights some of the best papers presented at the 32nd Symposium on VLSI Circuits, held on June 18–22, 2018, at the Hilton Hawaiian Village, Honolulu, HI, USA. Industry and university engineers from all over the world reported innovative new techniques and state-of-the-art results. Papers presented covered a broad range of topics important to VLSI circuit and system designers, including topics that are also important to integrated circuit technology developers.

Introduction to the Special Issue on the 2017 Symposium on VLSI Circuits

This Special Issue of the IEEE Journal of Solid-State Circuits highlights some of the best papers presented at the 31st Symposium on VLSI Circuits, held on June 5, 2017–June 9, 2017, at the Rihga Royal Hotel Kyoto in Kyoto, Japan. Industry and university engineers from all over the world reported innovative new techniques and state-of-the-art results. Papers presented covered a broad range of topics important to VLSI circuit and system designers, including topics also important to integrated circuit technology developers.

Design and Implementation of Power Efficient Modified Russian Peasant Multiplier using Ripple Carry Adder

FIR filters, microprocessor and digital signal processor are the core system of multipliers. MAC is the most important building block in DSP system. The key element of high throughput multiplier and accumulator unit (MAC) is to achieve a high-performance digital signal processing application. In this paper, Modified Russian Peasant Multiplier (MRPM) using Ripple Carry Adder (RCA) has been proposed. According to Russian Rule‟s, Divide and conquer technique is used in the multiplication process. But, in perspective of digital design, only shifters and adders are used in Russian Peasant Multiplier to produce Partial Product Generation (PPG). A ripple carry adder is a logic circuit in which the carry-out of each full adder is the carry in of the next most significant full adder. It is called a ripple carry adder because each carry bit gets rippled into the next stage. Here, ripple carry adder is used for low power application. Reducing the chip size, increasing the speed and reducing the power consumption are main crucial factors in VLSI System design environment. The goal of this research work is to design the VLSI implementation of MAC for high-speed DSP applications. For designing the Multiplication and accumulation unit, different kinds of multipliers and adders are considered in this paper. The total operation is coded with Verilog HDL using ModelSim 6.3C, synthesized by using Xilinx ISE 12.4i design tool.

Introduction to the Special Issue on the 2016 Symposium on VLSI Circuits

This Special Issue of the IEEE Journal of Solid-State Circuits highlights some of the best papers presented at the 30th Symposium on VLSI Circuits, held on June 14–17, 2016 at the Hilton Hawaiian Village, Honolulu, Hawaii. Industry and university engineers from all over the world reported innovative new techniques and state-of-the-art results. Papers presented covered a broad range of topics important to VLSI circuit and system designers, including topics also important to integrated circuit technology developers.

Editorial

As I start my second two-year term (2017–2018) as the Editor-in-Chief (EIC) of the IEEE Transactions on Very Large Scale Integration Systems (TVLSI), I wish the TVLSI readership a very happy new year and continued professional success. It gives me great pleasure to report on the state of the journal and our performance metrics. Over the past two years, TVLSI has seen a healthy increase in the number of submissions—from 687 in 2014 to 770 in 2015, and at the time of writing of this editorial, we are at 760 submissions for 2016. We expect the number of submissions for 2016 to cross 800 before the end of the year. TVLSI, therefore, continues to be the premier archival journal for university researchers and industry practitioners in the broad area of VLSI system design.

Introduction to the Special Issue on the 2015 Symposium on VLSI Circuits

The papers in this special section were presented at the 29th Symposium on VLSI Circuits, held on June 16–19, 2015 at the Rihga Royal Hotel Kyoto, Japan. Papers presented covered a broad range of topics important to VLSI circuit and system designers, including topics also important to integrated circuit technology developers.

Enhanced Approach of Spectral Clustering-Hybrid Mean Cut Balanced Clustering in VLSI Circuits-(SC-HMCBC)

In VLSI power system, clustering and system design become a major key for the consumption of power. Basically, clustering approach is used to generate the groups and consider for efficiency process in raising growth of IC and design. From various approaches based on simplicity and robustness the popular approach is considered with the improvement as a proposed approach of Hybrid Mean Cut Balanced clustering approach. The proposed approach is implemented in the application of VLSI circuits. In existing, the data points are split into subsets as per the associated points and the clustering center updating. Also, it avoids the sets to balance the target data sets. But in the proposed approach, the weighted undirected graph is implemented which will split the vertices into two sets and for balancing with accuracy the hybrid mean cut approach is implemented to control the clustering outcomes degree. According to the function optimization the clustering results are balanced and the extensive simulation in large sets of data is validated the performance improvement. The clustering design is stimulated using Cadence Virtuoso tool of 180nm gpdk library functions.