VLSI System Design Research Articles

Automatic layout synthesis of analog ICs using circuit recognition and constraint analysis techniques

A systematic method for automatic layout synthesis of analog integrated circuit modules is presented. This method uses analog circuit recognition and critical net analysis techniques to derive proper layout constraints for analog circuit performance optimization. These layout constraints are analyzed and prioritized according to the recognized analog circuit topologies and classified net sensitivities. The weighted constraints are then used to drive the physical layout generation process to obtain a high-quality custom circuit layout. An efficient, constraint-driven analog floorplanning technique based on a zone-sensitivity partitioning algorithm is specially developed to generate a slicing floorplan incorporating the layout constraints. This layout synthesis approach has three key advantages. First, it can produce a satisfactory analog circuit performance with negligible degradation due to the layout-introduced parasitic effects. Second, it allows a complete automation for netlist-to-layout synthesis so that the layout tool can be used by VLSI system designers. Finally, this method is quite general and can be applied to handle a wide variety of analog circuits. Experimental results in CMOS operational amplifiers and a comparator are presented.

The use of RTL descriptions in accurate timing verification and test generation (VLSI)

The authors discuss the use of high-level information in two major problems of VLSI system design: (1) accurate timing verification to eliminate false paths due to reconvergent fan-out, redundancy, and control signal constraints, and (2) testing for stuck-at-faults. The register-transfer-level (RTL) descriptions provide the set of control signals for valid data operations. Using this set of control signals, the timing verifier can perform an efficient estimation of critical path delays for only valid data transfers. This approach to critical path justification can be extended to test generation for a class of sequential circuits where all latches and memory elements can be explicitly identified. Test generation for complex VLSI circuits composed of many interconnected modules is discussed. Sequential propagation and justification of signals are carried out using the data flow information. Results based on an implementation of the algorithms are presented. >

An example of a new VLSI design style based on systolic macrocells: A high‐speed single‐chip transversal filter for signal processing applications

AbstractThis paper describes the VLSI design of a high‐speed single‐chip FIR filter for data with a limited number of bits. A new design style that allows easy design of high speed VLSI systems was used. This style is based on the extensive use of systolic arrays and it is well suited to VLSI system realizations for digital signal processing (DSP) applications. This realization shows that high performance systems can be obtained with a systolic approach, using a few main building blocks called macrocells, systolic at the bit‐level, of general use and easily interconnected.

Performance-directed synthesis of VLSI systems

The two tasks involved in the design of VLSI systems, synthesizing the circuit and then analyzing it to verify the desired behavior and performance, are becoming intertwined, and performance constraints are being used to drive synthesis. This approach requires the ability to explore efficiently many design options and to find global optima over the several consistently aligned representation levels simultaneously. General requirements for performance-directed synthesis are characterized, followed by an overview of algorithms used for performance optimizations both within and between the several levels of representation. The need for techniques for simultaneous constraint optimization and a perspicuous characterization of the total design space is highlighted. >

The DTI-industry sponsored Silicon Architectures Research Initiative

A significant national programme on the development of advanced software for VLSI system design is reported. The Silicon Architectures Research Initiative (SARI) is supported by selected UK electronics companies as well as the UK Department of Trade & Industry (DTI). It has resulted in the design and development of an interactive software suite for optimising a system implementation in VLSI circuit form. The new software permits a specific system design to be optimised in terms of chip speed or area prior to interfacing with one of the available commercial silicon layout tools.

Up Close: The Interuniversity Microelectronics Center (IMEC), Leuven, Belgium

The Interuniversity Microelectronics Center, Leuven, Belgium (IMEC) is one of the world's largest independent research centers for microelectronics. It was established in 1984 by the Flemish government as a part of a comprehensive program to promote high technology in Flanders, Belgium. Benefiting from existing experience available mainly at the University of Leuven, IMEC moved into its present facilities in 1986 (Figure 1).The Center covers a wide range of research topics in the microelectronics domain—VLSI systems design methodologies, advanced semiconductor processing, materials, packaging, and more.About 50 people work on computer-aided design, developing a series of “true” silicon compilers: CATHEDRAL. With this software, ASIC (application specific integrated circuit) design becomes extremely attractive, since CATHEDRAL covers design from the high system level down to layout.INVOMEC, the training division of IMEC, supports universities in ASIC design. It trains people for both educational institutes and industry in chip design, makes available the necessary software, and has a well-established Multi Project Chip—Multi Project Wafer service.The Processing Technologies and Materials Divisions involve about 200 people and have a 3,600 m2 clean room at their disposal. The clean room consists of a 20% class 10 area with a fast-turnaround prototyping line and an 80% class 1000 area.IMEC's objectives are: to perform research in the microelectronics field, supporting both industry and universities, and to stimulate the microelectronics industry in Flanders.IMEC performs research on both silicon and III-V technologies.

Guest Editorial

Click to increase image sizeClick to decrease image size Additional informationNotes on contributorsSurendra PrasadSurendra Prasad received the BTech degree in Electronics and Electrical Communication Engineering from the Indian Institute of Technology, Kharagpur, in 1969, and the M Tech and PhD degrees in Electrical Engineering from the Indian Institute of Technology, New Delhi, in 1971 and 1974, respectively.He has been teaching at the Indian Institute of Technology, New Delhi, since August 1971 where he is presently a Professor of Electrical Engineering. He was a visiting research fellow at the Loughborough University of Technology, Loughborough, England from August 1976 to August 1977, where he was involved in developing algorithms for adaptive array processing for high frequency arrays. He was also a visiting faculty member at the Pennsylvania State University, USA., from August 1985 to December 1986. His teaching and research interests include, communications, radar and sonar signal processing and computer aided design of digital and VLSI systems and has been a consultant to a number of Government agencies as well as industry in these and released areas. Currently, he is engaged in research in various aspects of Statistical Signal Processing, including among others the areas of Sonar and Seismic Signal Processing, Time Series Modeling, Underwater Acoustics, Array Signal Processing and Computer Architectures for Signal Processing.He was the recipient of the Vikram Sarabhai Research award in Electronics and Telecommunications for the year 1987 and the S S Bhatnagar Award for Engineering Science for 1988.

The Development of an Undergraduate Curriculum for VLSI Design

This contribution describes the way in which the ECAD facilities have been exploited in the development of an undergraduate curriculum for the teaching of IC design in an Electronic Systems B. Eng. degree scheme. The programme of course and laboratory work culminates in a final year core course in Microelectronic Circuit Technology and Design together with a specialist option in VLSI Systems Design which includes chip fabrication activities.

Block diagonal structure in discrete transforms

The author investigates and summarises some of the computational tasks of discrete transforms in which block diagonal structure plays a dominant role. Walsh-Hadamard transform (WHT) based algorithm designs for various well known discrete transforms are presented; it can be proved that, owing to their block diagonal structure, the WHT based discrete transforms are more efficient than those of the conventional radix-r algorithms for transforms of length N<or=64. It is proved that block diagonal structures exist in the running Walsh-Hadamard transform, the running discrete Hartley transform (DHT), and the running discrete cosine transform (OCT). With regard to block diagonal structure in the transform conversions between DHT and DCT, some existing research results are summarised, and an efficient architecture for generating multiple discrete transform simultaneously is proposed. The two-stage DFT algorithm proposed by O.K. Ersoy (1987) is extended to that of the DHT and it is proved that two stage DHTs possess a somewhat more interesting 'balanced-block-diagonal' structure. In the context of VLSI system design, two factors are of particular importance: the regularity of processor cells and local communication between processors. The hardware implementation of the block diagonal algorithm, for moderate N, just meets the above requirements. An example of the WHT/DHT is also included.

Book Review: Introduction to nMOS and CMOS VLSI Systems Design

Book Review: Introduction to nMOS and CMOS VLSI Systems Design

Computer Aided Tools for VLSI System Design

Computer Aided Tools for VLSI System Design

A Semicustom VLSI System Design Course Supported by the General Electric Microelectronics Center

This paper presents an approach to VLSI system design and fabrication using gate arrays which has been implemented at the University of Virginia in conjunction with the General Electric Microelectronics Center (GE-MEC). Material initially developed by GE-MEC was modified and incorporated into a new graduate course to supplement that which already existed in the area of VLSI system design. A software tool set which includes functional and fault simulators for the TEGAS <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TM1</sup> hardware description language, a testability analyzer, and packages for cell placement, channel routing, and system delay extraction was used for chip design. Chip fabrication of successful design projects is the responsibility of GE-MEC.

VLSI system design by the numbers : Gaetano Borriello, Randy H. Katz, Alan G. Bell and Lynn Conway. IEEE Spectrum 44 (February 1985)

VLSI system design by the numbers : Gaetano Borriello, Randy H. Katz, Alan G. Bell and Lynn Conway. IEEE Spectrum 44 (February 1985)

A new cell-based interconnection network

In this paper, a new 4 × 4 cell-based interconnection network is proposed. The four-input four-output basic cell structure is constructed based on the new proposed concept of a completely interconnected set. This new interconnection network possesses the following properties: (i) High pipelining and parallelism, (ii) programmability (iii) modularity, and (iv) systematic design, which are suitable for the design of VLSI systems.

VLSI system design by the numbers: Design frames and system kits promise to simplify the development of VLSI-based systems

Two new concepts for computer development now being developed are design frames and system kits. The design frames take care of the details of interfacing new integrated circuits with a standard bus, and system kits provide a hardware and software standard for prototypes consisting of one or many design-frame-based circuit boards. A system kit starts with the basic prototyping hardware required to build a complete computer system: card cages, power supplies, memory boards, and so forth. These off-the-shelf parts are chosen so that they can work together through standard bus protocols, circuit-board form factors, and software conventions. The prototyping hardware is then augmented by design frames-a special interfacing technique for closely integrating custom chips and printed-circuit boards into the system.

Book Review: VLSI Systems Design for Digital Signal Processing, Vol. I: Signal Processing and Signal Processors

Book Review: VLSI Systems Design for Digital Signal Processing, Vol. I: Signal Processing and Signal Processors

Managing VLSI complexity: An outlook

The nature of complexity in the context of VLSI circuits is examined, and similarities with the complexity problem in large software systems are discussed. Lessons learned in software engineering are reviewed, and the applicability to VLSI systems design is investigated. Additional difficulties arising in integrated circuits such as those resulting from their two-dimensionality and from the required interconnections are discussed. The positive aspects of VLSI complexity as a way to increase performance and reduce chip size are reviewed. With this discussion as a basis, the evolution of VLSI system design environments is outlined for the near-term, medium-term, and long-term future. The changing role of the designer is discussed. Recommendations are made for enhancements to our engineering curriculums which would provide the next generation of designers with skills relevant to managing VLSI complexity.

The MPC adventures: Experiences with the generation of VLSI design and implementation methodologies

During the early '70's, Carver Mead began a pioneering series of courses in integrated circuit design at Caltech, presenting the basics of industry MOS design practice at the time. Observing some of the students' successes in later doing projects using these basics, Mead sensed that it might be possible to create new, much simpler methods of IC design than those then used in industry. In the mid '70's, Carver Mead and Lynn Conway, and their research groups at Caltech and Xerox, began a collaboration to search for improved, simplified methods for VLSI system design. They hoped to create methods that could be very easily learned by digital system designers, but that would also allow to full architectural potential of silicon to be realized. Their research yielded important basic results during '76 and '77. In the summer of '77, they began writing the textbook Introduction to VLSI Systems, to document the new methods. In the late '70's, Lynn Conway realized the need for large-scale experimentation to further generate, test, and validate the methods. Conway began using novel methods within a systematic, rapidly expanding set of interactions with many universities throughout the United States. Students at these schools took courses using the evolving textbook, and then did design projects as part of those courses. The projects were implemented, and the resulting feedback was used to extend, refine, and debug the text, the courses, the university design environments, and the new design methods. As a result of the research methodology used, and the very large scale of the interactions with university community (via computer-communications networks), the Mead-Conway design methods evolved unusually rapidly, going from concept to integration within industry in just a few years. This talk tells the story of these events, focussing on the research methods used to generate, validate, and culturally integrate the Mead-Conway design methods.

Special Feature A VLSI Geometry Processor For Graphics

Emphasizing ease of scaling and sharing of design tools, a new approach to VLSI systems design may deliver inexpensive specialized hardware.

Color-mapping techniques for computer-aided design and verification of VLSI systems

Color raster-scan displays are often equipped with hardware for color transformation. Because the transformation can be redefined much more quickly than a full image can be computed (in a host) and subsequently displayed, it is preferable when possible to perform image operations by simply changing the mapping. Here an interactive layout system for NMOS VLSI is described which gives immediate feedback in color. Viewing modes are emphasized; opaque and translucent modes are discussed which allow the flexibility required for efficient understanding of the design by the designer. The color table is also used to help the designer detect violations of design rules; design rule violations can be readily detected when the transformation unit is used to highlight overlaps of selected VLSI layers or fringe structures derived from them. These color-mapping methods for man-machine interaction promise to enhance the productivity of the designer considerably, and they point the way to VLSI design systems of the future.