Design of Low Power SRAM Cell Using Adiabatic Logic

Abstract

In VLSI system design power consumption and energy dissipation are become more important. To optimize the power consumption we are using adiabatic logic which is having capability of reusing power. In this paper we proposed novel 7T SRAM cell using MCPL adiabatic logic. We compared the performance of energy dissipation and power consumption of conventional 7T SRAM and adiabatic SRAM. Furthermore, the conventional 6T,7T SRAM cell and the designs which are related are designed using FINFET devices to achieve low power.7T SRAM is more stable compared to 6T SRAM but due to excess transistor in 7T SRAM the power consumption will be more. SRAM cells are designed in cadence EDA environment and layouts for these circuits are carried out in cadence Assura tool.