VLSI Domain Research Articles

A new nano-design of 16-bit carry look-ahead adder based on quantum technology

There is a requirement and a desire to develop reliable and energy-efficient circuit designs that adapt to the expanding field of low-power circuit engineering in the VLSI domain based on nanotechnology. The quantum-dot cellular automata (QCA) technology possesses the potential to supplant the conventional, complementary metal-oxide-semiconductor (CMOS) technology in low-power nano-scale applications due to its diminutive cell dimensions, dependable circuitry architecture, and robust structural integrity. On the other hand, the carry look-ahead adder (CLA) is one of the vital circuits in digital processing utilized in diverse digital applications. In addition, for the design of this essential circuit, the occupied area and the delay play the primary role because using a simple formulation can reduce the occupied area, energy consumption, and the number of gates count. In the previous structures, high delay and use of traditional technology (like CMOS) caused an increase in the number of gate counts and occupied areas. Using QCA technology, simple quantum cells, and a low delay, all the previous shortcomings can be resolved to reduce the number of gate counts and low occupied area in the CLA circuit. This paper proposes a new method that helps the propagation characteristics generate suitable signals to reduce the number of gate counts based on adders in QCA technology. Several new blocks are used to design fast binary adders. Finally, an optimal four and 16-bit CLA circuit will be proposed based on the adder circuit. Furthermore, the execution and experimentation of outcomes are carried out utilizing QCADesigner-2.0.3. The simulation-based comparison of values justified the proposed design’s accuracy and efficiency. The simulation results demonstrate that the proposed circuit has a low area and quantum cell.

Design of Area Efficient Single Bit Comparator Circuit using Quantum dot Cellular Automata and its Digital Logic Gates Realization

Quantum Dot Cellular Automata or QCA is a promising transistor less nano-technology that is growing in popularity and it has the capability to replace the ubiquitous CMOS technology in the VLSI domain. The paper discussed the simple design of single bit comparator circuit using QCA. A single-bit comparator circuit compares its two inputs and indicates which one is larger or are they both equal. This paper has focused on creating an area efficient QCA comparator circuit and a comparative study of area consumption with the previously made designs. The designed comparator circuit is the most area-efficient design as it is made up of minimum possible number of cells. A Comparator is used in equality testers and many other digital communications The circuit proposed in this paper is a three layered circuit which can alternatively be used to realize the basic logic gates. The circuit can also be used as an alternative to the majority and universal gates in QCA.

WITHDRAWN: Design and execution of programmable logic device using quantum dot cellular automata

Abstract Quantum-dot Cellular Automata (QCA) is a nano scale which works out material that is being sight seen by researchers in the VLSI domain in order to reduce the CMOS transistors mount. In QCA, the elemental units of basic logic gates are QCA cells. During this work, a unique XOR/XNOR-functions like a gate with a pair of inputs, a single enable input and a result is proposed and designed in QCA nanotechnology. QCA circuits can be utilized to study and design PLD. This method presents rules for specialized architecture projects using programmable devices and a simulation engine is proposed to tune resource fully simulate circuits of QCA aimed for this construction. The presented cell structures are simulated (replicated) and tested by using the QCA designer tool. These designs are superior to the remaining designs in cell complexity, covered area.

Performance Analysis of 5:2 compressor with 58 transistors

In the present generation of VLSI domain, designing a circuit with less power, area, and delay has become challenge for every designer. In this article we have design and implemented a design for 5:2 compressor which is the vital component in CMOS multiplier circuits. The proposed compressor circuit design requires less transistor count i.e. 58 transistors. The Simulation results of proposed 5:2 compressor has substantially expanded the performance of power delay in contrast to earlier designs.

Forced stack sleep transistor (FORTRAN): A new leakage current reduction approach in CMOS based circuit designing

Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4- bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.

Filter Design Using FPGA Concepts in the VLSI Domain for High-Speed Computing Applications

This paper presents a novel method of the design & development of FPGA architectures for the filtering concept using FIR filters with symmetric signal extensions.

Comparison of Silicon and Silicon-Tungsten Disulphide Heterojunction Based Tub-type Back Gated MOSFET Using Non-Equilibrium Green’s Function

At nanoscale along with the failure of Metal oxide semiconductor field-effect transistor due to short channel effects, Silicon has raised as another bottleneck for researchers. In the last couple of decades, researchers have provided different solutions in the form of Graphene and Transition Metal Dichalcogenides materials. Each Graphene and Transition Metal Dichalcogenides has its own set of disadvantages like poor ION/IOFF ratio and lower carrier mobility and hence cannot be used individually. In this article, a tub type metal oxide semiconductor field-effect transistor is designed and for application of the device in a low power VLSI domain, the back-gated technique is used. Different device properties are studied first with a Silicon-based channel and then a Silicon-Tungsten Disulphide heterojunction channel. The selection of SiO2 as a gate insulator and contact material is also justified. This article shows that instead of using conventional Silicon-based devices it is better to use heterojunction devices, as they offer much lower OFF-state current and better linearity properties.

Towards Sustainable Integrated Model for Skill Development: A Collaborative Approach

Abstract Employability of Engineering graduates and their ability to deliver to the VLSI industry expectations after they are hired has been a matter of concern, engaging the attention of academics and industry alike on this issue. It is not a problem of quantity that the industry is facing but it is a problem of quality – the quality of VLSI education and quality of students getting through engineering institutions is poor. The important problem is, most VLSI companies are reluctant to hire freshers. This is because only few colleges in India have the infrastructure or specific courses related to VLSI domain. Universities don’t have specific courses related to VLSI in their curriculum. The solution for this employability issue is to offer good quality VLSI education with live hands on projects. In India VLSI talent is in short supply, it is not a problem of quantity, but the quality.The solution is to offer good quality VLSI education. To address these issues KLE Tech-IESA-SEER has collaborated for promoting skill set requirement through a set of courses. The courses are designed, delivered and assessed by in-house and industry-expert to build competence. The success story is the extensive industrial experience, internship opportunity and job in VLSI core companies.

Review of State-of-Art Image Restoration Techniques

In recent years, image processing is an essential technique for most of the applications such as business, government sectors, medial industry, cinema field, and etc. In image processing, most of the subdomains are there which helps to do their respective process. Among that, Image Restoration (IR) is one of the important domain which helps to retrieve the original image information from the noisy image. Normally, input image is affected by noise during the transmission. So, noise need to be removed to get the original input image information. In this paper, different kind of IR techniques are explained which is implemented in Field Programmable Gate Array (FPGA). In VLSI domain, FPGA is the important process which is used to identify the hardware utilization of the entire algorithm. The process and different methods of IR is studied in this paper.

Design and Enactment of Diverse Low Power Techniques Based Schmitt Trigger

In the present-day VLSI system, low power design plays a noteworthy role. As we know that, a circuit with higher power consumption can ruin the performance of the system because in the modern world most of the systems are portable. Subsequently, they are functioned by the batteries. Therefore, it is desirable to have a system which operates at lower supply voltages along with maintaining the performance of the system. This low power system can be attained by abating the leakages of the devices up-to an enormous magnitude. In the contemporary VLSI system, a major role is being contributed by the Schmitt trigger circuit. Schmitt trigger is fundamentally a comparator. It is implemented by using a positive feedback. The Schmitt trigger circuit is used in various devices such as buffer, sub-threshold SRAM, sensors and PWM circuit. It is also used in analog to digital converter. The most significant property of the Schmitt trigger is that they provide hysteresis in their voltage transfer curve. Consequently, they provide better noise immunity as compared to their counterparts. Therefore it becomes quite important to enhance the performance of the Schmitt trigger circuit. The power dissipation of the device can be minimized by minimizing the sub-threshold current. The Schmitt trigger circuit is very imperative in producing a clean pulse from the input signal comprising of noise. There are various applications of Schmitt trigger circuit such as in scheming the oscillator circuit, analog to digital converter, function generator, signal conditioning and numerous applications. Thus, it becomes noteworthy to boost its performance by plummeting the leakages and power consumption of the Schmitt trigger circuit. We have realized the Schmitt trigger circuit by the use of FinFET. Therefore, we have got some optimum output in the parameters such as hysteresis width, power consumption and total noise of the Schmitt trigger circuit, but the leakages have been augmented. Thereafter, we have implemented several techniques on the Schmitt trigger circuit to shrink the leakage current, leakage power and other parameters further. We have applied Self Controllable Voltage Level, Adaptive voltage level and MTCMOS technique on the Schmitt trigger circuit using FinFET to further augment the presentation. All the circuits have been simulated in the virtuoso tool of the cadence in 45 nm VLSI domain. We have applied 0.7 V of the supply voltage to perform the simulation and got some tremendous outcome.

A VLSI Based Framework for Iterative and Adaptive Based Image Filter for Impulse Noise Removal

Implementation of noise removal filter in a VLSI domain is important. As VLSI domain is suitable for image processing applications and most of the image processors are now replaced with high performance FPGA. The inbuilt memory (Block RAM and distributed RAM) available in the FPGA fabric are utilized to store a pixel window of considerable size. In this paper the authors propose a VLSI based framework for efficient implementation of the Adaptive maximum pixel based Noise detector (APMAD) based filters. The histogram calculation of the image is efficiently carried out using the existing memory in the FPGA and using the “read first” property of the FPGA RAM, a single pixel requires two clocks for updating the histogram. As the proposed algorithm is adaptive and iterative, only FPGA with rich internal memory (RAM) should be chosen as the utilization of external memory will add additional latency. The proposed algorithm is simulated in FPGA (XILINX 12.2 ISIM) environment. Performance evaluation of noise detector are calculated in terms of PFP and PFN and quantitative evaluation of the filter are measured viz PSNR and MSE.

Multilevel hypergraph partitioning: applications in VLSI domain

In this paper, we present a new hypergraph-partitioning algorithm that is based on the multilevel paradigm. In the multilevel paradigm, a sequence of successively coarser hypergraphs is constructed. A bisection of the smallest hypergraph is computed and it is used to obtain a bisection of the original hypergraph by successively projecting and refining the bisection to the next level finer hypergraph. We have developed new hypergraph coarsening strategies within the multilevel framework. We evaluate their performance both in terms of the size of the hyperedge cut on the bisection, as well as on the run time for a number of very large scale integration circuits. Our experiments show that our multilevel hypergraph-partitioning algorithm produces high-quality partitioning in a relatively small amount of time. The quality of the partitionings produced by our scheme are on the average 6%-23% better than those produced by other state-of-the-art schemes. Furthermore, our partitioning algorithm is significantly faster, often requiring 4-10 times less time than that required by the other schemes. Our multilevel hypergraph-partitioning algorithm scales very well for large hypergraphs. Hypergraphs with over 100 000 vertices can be bisected in a few minutes on today's workstations. Also, on the large hypergraphs, our scheme outperforms other schemes (in hyperedge cut) quite consistently with larger margins (9%-30%).

Efficient simulated annealing on fractal energy landscapes

We present a new theoretical framework for analyzing simulated annealing. The behavior of simulated annealing depends crucially on the ldŋergy landscape” associated with the optimization problem: the landscape must have special properties if annealing is to be efficient. We prove that certain fractal properties are sufficient for simulated annealing to be efficient in the following sense: If a problem is scaled to have best solutions of energy 0 and worst solutions of energy 1, a solution of expected energy no more than ɛ can be found in time polynomial in 1/ɛ, where the exponent of the polynomial depends on certain parameters of the fractal. Higher-dimensional versions of the problem can be solved with almost identical efficiency. The cooling schedule used to achieve this result is the familiar geometric schedule of annealing practice, rather than the logarithmic schedule of previous theory. Our analysis is more realistic than those of previous studies of annealing in the constraints we place on the problem space and the conclusions we draw about annealing's performance. The mode of analysis is also new: Annealing is modeled as a random walk on a graph, and recent theorems relating the “conductance” of a graph to the mixing rate of its associated Markov chain generate both a new conceptual approach to annealing and new analytical, quantitative methods. The efficiency of annealing is compared with that of random sampling and descent algorithms. While these algorithms are more efficient for some fractals, their run times increase exponentially with the number of dimensions, making annealing better for problems of high dimensionality. We find that a number of circuit placement problems have energy landscapes with fractal properties, thus giving for the first time a reasonable explanation of the successful application of simulated annealing to problems in the VLSI domain.

Analog-binary CCD correlator: A VLSI signal processor

Advanced analog-binary CCD correlators will be useful in spread spectrum communications and radar systems employing PRN codes. Increased code-length capability and on-chip support circuitry drive chip size and density into the VLSI domain. Designs of key sections of a 512-stage correlator are discussed. The chip measures nearly 400 by 300 mils and contains all circuits necessary to accept and store a reference code and compare it to a signal. In addition, it contains many support circuits including the clock logic and drivers, code load logic, and TTL-to-MOS converters. Design of the floating-gate tap structure minimizes code-dependent bias, harmonic distortion, and tap-to-tap nonuniformity, while holding power dissipation to 1 mW per tap. Electron-beam lithography was used to produce photomasks with low defect density and tight dimensional tolerances over the array.