Design of Area Efficient Single Bit Comparator Circuit using Quantum dot Cellular Automata and its Digital Logic Gates Realization

Abstract

Quantum Dot Cellular Automata or QCA is a promising transistor less nano-technology that is growing in popularity and it has the capability to replace the ubiquitous CMOS technology in the VLSI domain. The paper discussed the simple design of single bit comparator circuit using QCA. A single-bit comparator circuit compares its two inputs and indicates which one is larger or are they both equal. This paper has focused on creating an area efficient QCA comparator circuit and a comparative study of area consumption with the previously made designs. The designed comparator circuit is the most area-efficient design as it is made up of minimum possible number of cells. A Comparator is used in equality testers and many other digital communications The circuit proposed in this paper is a three layered circuit which can alternatively be used to realize the basic logic gates. The circuit can also be used as an alternative to the majority and universal gates in QCA.