CMOS VLSI Circuits Research Articles

Compact low power high slew rate CMOS buffer for large capacitive loads

A new compact CMOS class AB buffer for capacitive loads is presented. Its simple implementation relies on the use of the flipped voltage follower. Simulation results from a 0.35 µm CMOS technology are presented that prove the operating principle under low power conditions. This buffer can also find application in testing of analogue CMOS VLSI circuits, as the input capacitance can be very low without diminishing its output drive capability.

Fault security analysis of CMOS VLSI circuits using defect-injectable VHDL models

This paper introduces a methodology for assessing the fault security attributes of Fault Secure (FS) circuits. Structural VHDL circuit descriptions are used to simulate the fault effects of realistic transistor level defects that occur in CMOS ICs. Defective standard cells are simulated at the analog level of abstraction and the resultant fault effects are implemented in defect-injectable VHDL models to allow logic simulation. Typical fault effects include functional changes, propagation delay increases, sequential logic faults, stuck-at faults, reduced noise margins, and increased I DDQ. The defect-injectable VHDL models are swapped into FS circuit designs and the effects of the defects are analyzed in the context of the digital circuit. The FS circuits can then be assigned a figure of merit based on the ratio of detected defects to those that actually cause output errors. To facilitate the execution of the methodology, an integrated software tool has been developed that, in combination with a commercial VHDL simulation tool, provides an automated means for determining the figure of merit. Implemented using a GUI, the new tool is user friendly and flexible enough to be used with various logic circuits and different IC technologies. Three different checker, as benchmarks, wére evaluated to demonstrate the FSA tool and the methodology to assess their relative fault security.

Microsystem optoelectronic integration for mixed multisignal systems

The integration and packaging of optoelectronic devices with electronic circuits and systems has growing application in many fields, ranging from long to micro haul links. An exploration of the opportunities, integration technologies, and some recent results using thin-film device heterogeneous integration with Si CMOS VLSI and GaAs MESFET circuit technologies are presented. Applications explored include alignment tolerant optoelectronic links for network interconnections, smart pixel focal plane array processing through the integration of imaging arrays with sigma delta analog to digital converters underneath each pixel, and three-dimensional computational systems using vertical through-Si optical interconnections.

Capteurs intelligents par réseaux de neurones: l'exemple d'un microsystème d'inspection visuelle [Intelligent sensors using neural networks: the example of a microsystem for visual inspection

The aim of this article is to show how artificial neural networks and 3D packaging technology have a major role to play in the development of microsystems. A visual inspection system for real-time identification of objects in a scene is described. The system comprises a CMOS or CCD imager, an analogue preprocessing stage that includes a learning mechanism for adapting the system to images of different contrast, and a neural classification stage. The detection of a matrix code using as the classifier a vector support machine is illustrated. As the latter is difficult to realise in VLSI the author has turned to the threshold neural network `Offset', which constructs a parity machine, i.e. a network comprising a single layer of neurons, the output being obtained with the help of a simple exclusive-OR logic gate. Unfortunately the parity machine suffers from overtraining, as the OffSet algorithm converges to a zero error over the entire training base. Nevertheless, if good implementation strategies are available, it is possible to improve the performance in general by combining a large number of classifiers by majority voting. A CMOS VLSI circuit, called SysNeuro, has been fabricated which integrates a parity machine in a square systolic architecture of 4×4 processors. This circuit has variable precision. The number of neurons has been increased by combining 4 SysNeuro chips in a multichip module and stacking three of the modules to form a 3D structure-SysNeuro3D.

A resistor/transconductor network for linear fitting

We present a continuous time analog VLSI CMOS circuit consisting of resistors and transconductors for computing the best-fit line to a set of data points. The circuit can implement standard least-squares linear fitting, as well as a form of linear fitting that is more robust to outliers. We analyze the static and transient response of the chip, and present design criteria given desired constraints on speed and accuracy. Finally, we describe the transistor level design and measurement results from a 50-input prototype fabricated using a 1.2 /spl mu/m n-well process.

Fault model for sub-micron CMOS ULSI circuits reliability assessment

A new fault model, based on the general Percolation theory applied to long-channel CMOS VLSI circuits, has been recently introduced. It was shown that a reliability risk appears only when process-related defects create a pattern independent current path in standby mode. An acceptable reliability risk defines pass/fail criteria. A screening technique, based on this model, presents a strong correlation between rejected devices and Early Failure Rate. In this paper, the general Percolation approach was applied to short-channel CMOS VLSI circuits. Unlike long-channel CMOS VLSI, defect-free short-channel CMOS VLSI circuits inherently have a pattern-independent standby current. It results from a short-channel MOSFET current in the off state. In this case, the defect-related component of this current might be released only by means of a multi parameter fail criterion. Experimental results that confirm this conclusion are presented and discussed. The Reliability Risk assessment technique employing this model shows a strong correlation between rejected devices and long term reliability for 32-bit 0.35 μM CMOS microprocessors.

A New Statistical Method for Maximum Power Estimation in CMOS VLSI Circuits

A method for maximum power estimation in CMOS VLSI circuits is proposed. The method is based on extreme value theory and allows for the calculation of the upper end point of the probability distribution which is followed by the instantaneous power drawn from the supply bus. The main features of the method are the relatively small and circuitin-dependent subset of input patterns required for accurate prediction of maximum power and its simulative nature which ensures that no over-simplifying assumptions are made. Application of the proposed method to eight distributions, which come close to the behavior of power consumption in VLSI circuits, proved its superior capabilities with respect to existing methods.

Design and Realization of a Built-In Current Sensor for I _DDQ Testing and Power Dissipation Measurement

Built-in current sensor (BICS) is known to enhance test accuracy, defect coverage of quiescent current (I_{DDQ}) testing method in CMOS VLSI circuits. For new deep-submicron technologies, BICSs become essential for accurate and practical I_{DDQ} testing. This paper presents a new BICS suitable for power dissipation measurement and I_{DDQ} testing. Although the BICS presented in this paper is dedicated to submicron technologies that require reduced supply voltage, it can also be used for applications and technologies requiring normal supply voltage. The proposed BICS has been extended for on-line measurement of the power dissipation using only an additional capacitor. Power dissipation measurement is important for safety-critical applications and battery-powered systems. A simple self-test approach to verify the functionality and accuracy of BICSs has also been introduced. The proposed BICS has been implemented and tested using an N-well CMOS 1.2 μm technology. Practical results demonstrate that a very good measurement accuracy can be achieved.

A new on-chip interconnect crosstalk model and experimental verification for CMOS VLSI circuit design

A new, simple closed-form crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance. CMOS device nonlinearity is simply approximated as a linear device. That is, the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further, while existing models do not support the multiple line crosstalk behaviors, our model can be generalized to multiple lines. That is, unlike previously published work, even if the geometrical structures are not identical, it can accurately predict crosstalk. The model is experimentally verified with 0.35-/spl mu/m CMOS process-based interconnect test structures. The new model can be readily implemented in CAD analysis tools. This model can be used to predict the signal integrity for high-speed and high-density VLSI circuit design.

Experimental results on BIC sensors for transient current testing

In this work experimental results on a built in current sensor for dynamic current testing, i/sub ddt/, based on integration concepts are presented. The experimental validation proposed in this work is done through a VLSI CMOS circuit implemented in a 0.7 micron technology. Different experiences have been developed analyzing the detectability of several kind of defects through this technique. The encouraging results obtained present this technique as an attractive complement to boolean and I/sub DDQ/ testing.

An Accumulator-Based BIST Approach for Two-Pattern Testing

Two-pattern tests target the detection of most common failure mechanisms in cmos vlsi circuits, which are modeled as stuck-open or delay faults. In this paper the Accumulator-Based Two-pattern generation (ABT) algorithm is presented, that generates an exhaustive n-bit two-pattern test within exactly 2^n × (2^n − 1) + 1 clock cycles, i.e. within the theoretically minimum time. The ABT algorithm is implemented in hardware utilizing an accumulator whose inputs are driven by either a binary counter (counter-based implementation) or a Linear Feedback Shift Register (LFSR-based implementation). With the counter-based implementation different modules, having different number of inputs, can be efficiently tested using the same generator. For circuits that do not contain counters, the LFSR-based implementation can be implemented, since registers (that typically drive the accumulator inputs into dapatapath cores) can be easily modified to LFSRS with small increase in the hardware overhead. The great advantage of the presented scheme is that it can be implemented by augmening existing datapath components, rather than building a new pattern generation structure.

ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips

In this paper, we present a new chip-level electrothermal timing simulator for CMOS VLSI circuits. Given the chip layout, the packaging specification, and the periodic input signal pattern, it finds the on-chip steady-state temperature profile and the resulting circuit performance. A tester chip has been designed for verification of ILLIADS-T, and very good agreement between simulation and experiment was found. Using this electrothermal simulator, temperature-dependent reliability and timing problems of VLSI circuits can be accurately identified.

Integration of CMOS-VLSI and light emitting sourcesby capacitive coupling

A novel principle is proposed for integration of III-V light sources with CMOS VLSI circuits. The flipped III-V chip is connected to the CMOS chip by capacitive coupling instead of by a conductive connection method. Energy is transmitted through a dielectric connection layer using a high frequency carrier signal. The proposed system requires no post-processing of the CMOS circuits and offers potentially high reworkability and good coupling efficiency.

CMOS VLSI reliability test model

This paper introduces a Fault Model capable of elucidating the sensitivity to Early Fault (EF) rising nature in CMOS VLSI circuits. The Model is based on the general Percolation Theory applied to the CMOS technology. CMOS VLSI circuit in steady state is represented as a non conductive network spread out between power supply, ground and input/output terminals. According to the percolation theory, in such a network there is a definite critical number of conductive defects that cause a permanent current path creation. The percolation current through this path applies a heavy stress condition to the circuit elements, causing their degradation. Early Failures screening technique employing this model, show a strong correlation between rejected devices and EF rate and the common nature of sensitivity to EOS and EF. This technique is pattern independent, cost and time efficient and does not expose tested devices to any stress conditions. It is recommended, both as an EF screening test and a process reliability monitor.

ITEM: a temperature-dependent electromigration reliability diagnosis tool

In this paper, we present a new electromigration reliability diagnosis tool (iTEM) for CMOS VLSI circuits. Unlike previous electromigration reliability tools, iTEM can estimate the interconnect temperature rise due to joule heating and heat conduction from the substrate using a newly developed lumped thermal model. By including the temperature effect, iTEM provides much more accurate electromigration reliability diagnosis. Moreover, it is computationally efficient, and can analyze circuit layouts containing tens of thousands of transistors on a desktop workstation.

Computer-aided redesign of VLSI circuits for hot-carrier reliability

In this paper, a computer-aided design system for CMOS VLSI circuit hot-carrier reliability estimation and redesign is presented. The system first simulates a circuit to determine the critical transistors that are most susceptible to hot-carrier effects (HCEs). It then estimates the impact of HCE on circuit performance and employs a combination of design modification strategies to eliminate HCE-induced performance degradation. Two criteria are used to evaluate HCE degradation. The first criterion is the estimation of local damage in each transistor, which indicates the possibility of failure of individual devices. The second criterion is the global degradation of the circuit, namely the increase of delay in digital circuits. If either criterion exceeds a user-specified limit, several alternative circuit redesign strategies can be chosen by the user from a suggested menu. Based on this choice, the system will automatically redesign the critical parts of the circuit to improve circuit performance. The advantages and disadvantages of these alternative redesign strategies are also compared.

Bridging defects resistance in the metal layer of a CMOS process

The resistance value of bridging defects in CMOS VLSI circuits are evaluated through a set of measurements performed on process-related defect monitoring wafers. The monitor circuits considered are made of metal1 lines. The results show how the vast majority of the measured metal1 to metal1 bridges has a low resistance. Only a small percentage of the overall bridges resulted in a resistance value above 500 Ω, while the exact percentage can vary from batch to batch. This high resistance does not seem to be the result of the material of the defect itself, since all these bridging defects were found to be caused by extra aluminium. The shape and location of the defect seem to be the cause of the high resistance values probably caused by poor contacts between the extra metal and the designed monitor lines.

Detection of multiple faults using SSFTS in CMOS logic circuits

With the increasing density of CMOS VLSI circuits, it is necessary to test for the combinations of different multiple faults. This paper studies the possibility of using single stuck-at fault test set (SSFTS) to detect multiple faults and their combinations. The paper shows that a single stuck-at-fault test set can detect single and multiple self-feedback bridging faults, combinations of feedback bridging, input bridging and stuck-on faults when current monitoring is done. We also prove that a single stuck-at fault test set can detect the combination of single stuck-open fault and some other faults like bridging and stuck-on faults when both logic and current monitoring are done.

Optoelectronic system integration on silicon: waveguides, photodetectors, and VLSI CMOS circuits on one chip

Optical waveguides, photodetectors, and VLSI CMOS circuits are integrated monolithically in different ways: in a combined integration technique the light-guiding film is deposited and covered with a SiO/sub 2/ layer replacing standard PSG as the dielectric insulation of polysilicon and metallization. In a stacked method the waveguide fabrication starts after metallization and test of the CMOS circuits. Electrooptical coupling is performed by butt-, leaky wave-, or, mirror-coupling of waveguides and photodetectors. To fabricate the system, SWAMI LOCOS technique is applied for monolithic integration of both, integrated optical devices, and microelectronic circuits. This paper discusses the integration technology and the results of static and dynamic measurements. >

Transient power supply current monitoring?A new test method for CMOS VLSI circuits

We present a new method for testing digital CMOS integrated circuits. The new method is based on the following premise: monitor the switching behavior of a circuit as opposed to the output logic state. We use the transient power supply current as a window of observability into the circuit switching behavior. A method for isolating normal switching transients from those which result from defects is introduced. The feasibility of this new testing approach is investigated by conducting several experiments involving the design of integrated circuits with built-in defects, fabrication, and physical testing. The results of these experiments show this new test method to be a promising one for detecting defects that can escape stuck-at testing andI DDQ testing.