Bridging defects resistance in the metal layer of a CMOS process

Abstract

The resistance value of bridging defects in CMOS VLSI circuits are evaluated through a set of measurements performed on process-related defect monitoring wafers. The monitor circuits considered are made of metal1 lines. The results show how the vast majority of the measured metal1 to metal1 bridges has a low resistance. Only a small percentage of the overall bridges resulted in a resistance value above 500 Ω, while the exact percentage can vary from batch to batch. This high resistance does not seem to be the result of the material of the defect itself, since all these bridging defects were found to be caused by extra aluminium. The shape and location of the defect seem to be the cause of the high resistance values probably caused by poor contacts between the extra metal and the designed monitor lines.