VLSI Array Research Articles

New Systolic Array Algorithms and VLSI Architectures for 1-D MDST

In this paper, we present two systolic array algorithms for efficient Very-Large-Scale Integration (VLSI) implementations of the 1-D Modified Discrete Sine Transform (MDST) using the systolic array architectural paradigm. The new algorithms decompose the computation of the MDST into modular and regular computational structures called pseudo-circular correlation and pseudo-cycle convolution. The two computational structures for pseudo-circular correlation and pseudo-cycle convolution both have the same form. This feature can be exploited to significantly reduce the hardware complexity since the two computational structures can be computed on the same linear systolic array. Moreover, the second algorithm can be used to further reduce the hardware complexity by replacing the general multipliers from the first one with multipliers with a constant that have a significantly reduced complexity. The resulting VLSI architectures have all the advantages of a cycle convolution and circular correlation based systolic implementations, such as high-speed using concurrency, an efficient use of the VLSI technology due to its local and regular interconnection topology, and low I/O cost. Moreover, in both architectures, a cost-effective application of an obfuscation technique can be achieved with low overheads.

A high-performance VLSI array reconfiguration scheme based on network flow under row and column rerouting

The reconfiguration algorithms have been extensively investigated to ensure the reliability and stability for the processor arrays with faults. It is important to reduce the power consumption, capacitance and communication costs in the processors by reducing the interconnection length of the VLSI array. This paper discusses the reconfiguration problem of the high-performance VLSI processor array under the row and column rerouting constraints. A novel method, making use the idea of network flow, is proposed in this paper. Firstly, a network flow model of the VLSI processor array is constructed, such that the high-performance VLSI target array can be obtained by utilizing the minimal cost flow algorithm. Secondly, we propose a new strategy for bottleneck row selection in the logical array using the minimum cut technique, which can find a more suitable bottleneck row. Finally, we conducted reliable experiments to clearly reveal the efficiency of the new rerouting scheme and algorithm in reducing the number of long interconnects. The experimental results show that, for a host array with size of 256×256, the number of long interconnects in the subarray can be reduced by up to 79.22% and 55.88% without performance penalty for random faults with density of 1% and 25% respectively, when compared with state-of-the-art. In addition, the proposed scheme improves existing algorithm in terms of subarray size. On a 256×256 host array with 25% faulty density, the average improvement in subarray size is up to 3.77% compared with state-of-the-art.

A mathematical programming method for constructing the shortest interconnection VLSI arrays

Mesh-connected processor array is an extensively investigated architecture in parallel processing. Massive studies have addressed the problem of using reconfiguration algorithms to solve the fault tolerance of faulty mesh-connected processor arrays. However, the subarrays generated by the previous studies still contain large interconnection length, which will lead to the increase of capacitance, power dissipation and dynamic communication cost. First, a mathematical model is established for the array reconfiguration. Then, the proposed method treats the interconnections between each PEs as a function with different integer variables, which can be solved by using effective integer programming techniques. Finally, an effective solver is called to find the optimal solution. Simulation results show that the proposed method can reduce the interconnection length of the array in the row and column directions simultaneously, thereby generating a subarray with the shortest interconnection length. On a 32 × 32 host array with fault density of 30%, the total interconnection length of the subarray can be reduced by 8.36% compared with state-of-the-art, and the average interconnection length can be reduced by 39.30%, which is more closer to the lower bound.

An improved algorithm for accelerating reconfiguration of VLSI array

Reducing the number of visits to failure-free nodes can effectively reduce the reconstruction time of logical columns and improve the reconstruction efficiency. In this paper, we describe a new method to speed up the reconfiguration for the VLSI arrays. An efficient algorithm was proposed based on shortest path first principle for accelerating reconfiguration of VLSI processor subarrays with high power efficiency to meet the requirement of the power consumption of embedded system. The proposed algorithm greatly reduces the number of visits to the fault-free PEs for constructing a local optimal logical column and effectively reduces the construction time. Experimental results show that the proposed algorithm is capable of reducing the consumption time by 32.15% and reducing the numbers of visited PEs by 49.61% for a 128 × 128 host array with 20% falut rate.

An efficient multiple shortest augmenting paths algorithm for constructing high performance VLSI subarray

Reconfiguring a high-performance subarray of a VLSI array with faults is to construct a maximum target array with the minimum number of long interconnects, which can reduce communication costs, capacitance and dynamic energy dissipation. An existing work proved that the high performance VLSI subarray can be constructed in polynomial time using network flow algorithm. However, because of the disadvantage of the previous network model and the low-performing of standard network flow algorithms for reconfiguration, the efficiency of these algorithms is poor for constructing the high performance VLSI subarray. In this paper, we present an efficient multiple shortest augmenting paths algorithm for rapidly constructing high performance VLSI array. Firstly, we proposed an efficient data structure to construct the network model of the VLSI array with faults, which can dramatically reduce the size of the model compared with previous algorithm. Secondly, a multiple shortest augmenting path algorithm based on the new data structure is proposed, which can significant reduce the running time. Finally, we conduct solid experiments to highlight the efficiency of the proposed method in terms of the running time compared to the standard network flow algorithms. The experimental results show that on a 64 × 64 host array with 0.1% faults, the size of the network model can be reduced by about 50% and the average improvements in running time is up to 85.10% compared with four standard network flow algorithms.

Accelerating reconfiguration for VLSI arrays with A‐Star algorithm

We describe a novel technique to speed up the reconfiguration for the very large scale integration (VLSI) arrays. We propose an efficient algorithm, making use of the idea of the A‐star algorithm, for accelerating the reconfiguration of the VLSI processor arrays to meet the real‐time constraints of embedded systems. The proposed algorithm treats the problem of constructing a local optimal logical column that has the minimum number of long interconnects as a shortest path problem. Then the local optimal column can be constructed by utilizing the A‐star algorithm with the appropriate heuristic strategy. We prove that the proposed method can find the shortest local logical column. Simulation experiments reveal that the proposed algorithm can greatly reduce the number of visits to the fault‐free processing elements (PEs) for constructing a local optimal logical column and effectively decrease the reconfiguration running time. Experimental results show that the computation time can be reduced by more than 38.64% for a 128 × 128 host array with fault density of 20%, without loss of harvest. © 2018 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

A New Systolic Array Algorithm and Architecture for the VLSI Implementation of IDST Based on a Pseudo-Band Correlation Structure

In this paper a new linear VLSI array architecture for the VLSI implementation of a prime-length 1-D Inverse Discrete Sine Transform (IDST) is proposed. This new design approach uses a ...

Satisfiability-based method for reconfiguring power efficient VLSI array

Satisfiability-based method for reconfiguring power efficient VLSI array

CONSTRUCTING LOW-TEMPERATURE SUB-ARRAYS ON RECONFIGURABLE VLSI ARRAYS

Increasing temperatures of the processing elements (PEs) on VLSI may threaten the reliability and performance of a hard real-time system. This paper presents a temperature-aware algorithm to reconfigure two-dimensional VLSI arrays in the presence of faulty PEs. Based on dynamic programming, the proposed algorithm constructs each logical column with the lowest temperature for a cool target array on a given processor array. In addition, the lower bound of the temperatures of the cool target array has been established. Simulation results show that the temperatures of target array are reduced without loss of harvest in comparison to the state-of-the-art. Moreover, the produced peak temperature of cool target array is pretty close to the lower bound.

Constructing Sub-Arrays with ShortInterconnects from Degradable VLSI Arrays

Reducing the interconnection length of VLSI arrays leads to less capacitance, power dissipation and dynamic communication cost between the processing elements (PEs). This paper develops efficient algorithms for constructing tightly-coupled subarrays from the mesh-connected VLSI arrays with faulty PEs. For a given size r·s of the target (logical) array, the proposed algorithm searches and reroutes a physical r×s subarray that has the least number of faults, resulting in an approximate target array, which is subsequently extended to the desired target array. Experimental results show that over 65 percent redundant interconnects can be reduced for a 64×64 target array on the 512×512 host array with no more than 1 percent faults. In addition, we propose a recursive divide-and-conquer algorithm for constructing the maximum target array (MTA). The lower bound of the total interconnection length of the MTA has been established. Experimental results show that the proposed algorithm is capable of reducing the long interconnects by over 33 percent for the MTA derived from the 512×512 host array with no more than 1 percent faults. Moreover, the proposed total interconnection length of target array is close to the lower bound for the cases with relatively fewer number of faults.

0.18 μm CMOS proess high-sensitivity optially reonfgurable gatearray VLSI

Currently, demand for high-speed dynamic reconfiguration of a programmable device is increasing for the purpose of increasing the performance of such devices. To support the high speed dynamic reconfiguration, optially reconfigurable gate arrays (ORGAs) have been developed up to now. An ORGA consists of a holographic memory, a laser array, and an optially reconfigurable gate array VLSI. The holographic memory can store many configuration contexts. In addition, its large bandwidth optical connection enables high speed reconfiguration. However, photodiode sensitivities of conventional ORGAs were not good. This paper therefore presents a newly fabriated 0.18πm CMOS process optially reconfigurable gate array VLSI chip with highly sensitive photociruits.

Scalable linear array architectures for matrix inversion using Bi-z CORDIC

In this paper, VLSI array architectures for matrix inversion are studied. A new binary-coded z-path (Bi-z) CORDIC is developed and implemented to compute the operations required in the matrix inversion using the Givens rotation (GR) based QR decomposition. The Bi-z CORDIC allows both the GR vectoring and rotation mode, as well as division and multiplication to be executed in a single unified processing element (PE). Hence, a 2D (2 dimensional) array consisting of PEs with different functionalities can be folded into a 1D array to reduce hardware complexity. The Bi-z CORDIC also eliminates the arithmetic complexity of the angle quantization and formation computation that exist in the traditional CORDIC. Two mapping techniques, namely a linear mapping method and an interlaced mapping method, for mapping a 2D matrix inversion array into a 1D array are proposed and developed. Consequently two corresponding array architectures are designed and implemented. Both the architectures use the Bi-z CORDIC in their PEs and they are designed to be fully scalable and parameterizable in terms of matrix size and data wordlength. The linear mapping method is a straightforward mapping offering simple schedule and control signals. The interlaced mapping method has a more complicated schedule with complex control signals but achieves 100% or near 100% processor utilization for odd and even size matrix, respectively.

Fast Optical Reconfiguration of a Nine-Context DORGA Using a Speed Adjustment Control

Demand for fast dynamic reconfiguration has increased since dynamic reconfiguration can accelerate the performance of implementation circuits. Such dynamic reconfiguration requires two important features: fast reconfiguration and numerous reconfiguration contexts. However, fast reconfiguration and numerous reconfiguration contexts share a trade-off relation on current VLSIs. Therefore, Optically Reconfigurable Gate Arrays (ORGAs) have been developed to resolve this dilemma. An ORGA architecture allows many configuration contexts by exploiting the large storage capacity of a holographic memory and fast reconfiguration using wide-bandwidth optical connections between a holographic memory and a programmable gate array VLSI. In addition, Dynamic Optically Reconfigurable Gate Arrays (DORGAs) using a photodiode memory architecture have already been developed to realize a high-gate-density VLSI. Therefore, this article presents the first demonstration of a nanosecond-order configuration of a nine-context DORGA architecture. Moreover, this article presents a proposal of a reconfiguration period adjustment technique to control each reconfiguration period to its best setting.

Novel VLSI Algorithm and Architecture with Good Quantization Properties for a High-Throughput Area Efficient Systolic Array Implementation of DCT

Using a specific input-restructuring sequence, a new VLSI algorithm and architecture have been derived for a high throughput memory-based systolic array VLSI implementation of a discrete cosine transform. The proposed restructuring technique transforms the DCT algorithm into a cycle-convolution and a pseudo-cycle convolution structure as basic computational forms. The proposed solution has been specially designed to have good fixed-point error performances that have been exploited to further reduce the hardware complexity and power consumption. It leads to a ROM based VLSI kernel with good quantization properties. A parallel VLSI algorithm and architecture with a good fixed point implementation appropriate for a memory-based implementation have been obtained. The proposed algorithm can bemapped onto two linear systolic arrays with similar length and form. They can be further efficientlymerged into a single array using an appropriate hardware sharing technique. A highly efficient VLSI chip can be thus obtained with appealing features as good architectural topology, processing speed, hardware complexity and I/O costs. Moreover, the proposed solution substantially reduces the hardware overhead involved by the pre-processing stage that for short length DCT consumes an important percentage of the chip area.

Dynamic optically reconfigurable gate array very large-scale integration with partial reconfiguration capability

We present a proposal of a partial reconfiguration architecture for optically reconfigurable gate arrays and present an 11,424 gate dynamic optically reconfigurable gate array VLSI chip that was fabricated on a 96.04 mm(2) chip using an 0.35 μm three-metal complementary metal oxide semiconductor process technology. The fabricated VLSI chip achieved a 2.21 μs partial reconfiguration.

Superimposing acceleration and optimization method of optical reconfiguration speed without any increase of laser power

This paper proposes a method of superimposing acceleration and optimizing the optical reconfiguration speed while requiring no increase of laser power. Using this technique, the optical reconfiguration speed is increased by superimposing multiple configuration contexts. Simultaneously, optimization of the number of configuration contexts and reconfiguration speed is possible. A full four-context optically reconfigurable gate array system consisting of an optically reconfigurable gate array VLSI, an easily rewritable liquid crystal holographic memory, and four vertical-cavity surface-emitting lasers was constructed to demonstrate this method. This paper clarifies the method's benefits using experimental results obtained from the demonstration system.

Preprocessing and Partial Rerouting Techniques for Accelerating Reconfiguration of Degradable VLSI Arrays

This paper presents novel techniques to accelerate the reconfiguration of degradable very large scale integration arrays. A preprocessing step is used to derive the upper and lower size bounds of the maximum logical array (MLA) such that only those subarrays that possibly contain the MLA are reconfigured, thereby reducing the reconfiguration time and also obtaining a same-sized logical array. In addition, the partial rerouting approach is generalized so that as many as possible previous routing results can be reused in the current rerouting step. The reconfiguration time is reduced from O((1-?)·s·m ·n) to its lower bound O((1-?)·m·n) for m × n host arrays with small fault density ?, where s is the expected routing length required per logical column.

Minimizing interconnect length on reconfigurable meshes

Shorter total interconnect and fewer switches in a processor array definitely lead to less capacitance, power dissipation and dynamic communication cost between the processing elements. This paper presents an algorithm to find a maximum logical array (MLA) that has shorter interconnect and fewer switches in a reconfigurable VLSI array with hard/soft faults. The proposed algorithm initially generates the middle (⌊k/2⌋th) logical column and then makes it nearly straight for the MLA with k logical columns. A dynamic programming approach is presented to compact other logical columns toward the middle logical column, resulting in a tightly-coupled MLA. In addition, the lower bound of the interconnect length of the MLA is proposed. Experimental results show that the resultant logical array is nearly optimal for the host array with large fault size, according to the proposed lower bound.

Programmable optically reconfigurable gate array architecture and its writer

Recently, optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser array, have been developed to achieve huge virtual gate counts that vastly surpass those of currently available VLSIs. By exploiting the large storage capacity of a holographic memory, VLSIs with more than 1 teragate counts will be producible. However, compared with current field programmable gate arrays, conventional ORGAs have one important shortcoming: they cannot be reprogrammed after fabrication. To reprogram ORGAs, a holographic memory must be disassembled from its ORGA package, then reprogrammed outside of the ORGA package using a holographic memory writer. It must then be implemented onto the ORGA package with high precision techniques beyond that which can be provided by manual assembly. Therefore, to improve this shortcoming, this paper proposes what is believed to be the world's first programmable ORGA architecture with no disassembly. Finally, the availability of this architecture is discussed based on the experimental results.

A Dynamic Optically Reconfigurable Gate Array—Perfect Emulation

This paper presents a perfect dynamic optically reconfigurable gate array (DORGA) architecture emulation using a holographic memory and a conventional ORGA-VLSI. In ORGAs, although a large virtual gate count can be realized by exploiting the large-capacity storage capability of a holographic memory, the actual gate count, which is the gate count of a programmable gate array VLSI, is important to increase the instantaneous performance. Nevertheless, in previously proposed ORGA-VLSIs, the static configuration memory to store a single configuration context consumed a large implementation area of the ORGA-VLSIs and prevented the realization of large-gate-count ORGA-VLSIs. Therefore, a DORGA architecture has been proposed in order to increase the gate density. It uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However, to date, demonstration of a perfect optically reconfigurable architecture for DORGA-VLSIs has never been presented. Therefore, in this study, the DORGA architecture was perfectly emulated, and the performance, particularly the reconfiguration context retention time, was measured experimentally. The advantages of this architecture are discussed in relation to the results.