VLSI Array Research Articles

FAULTS IN FUZZY LOGIC SYSTOLIC ARRAYS

Systolic VLSI arrays have been proposed for fast fuzzy inference processes in control systems Due to their complexity. VLSI circuits sometimes fail and the result is an erroneous output. In this paper, faults in fuzzy logic systolic arrays are considered. It will be shown that a single fault in the array may complement the fuzzy output. Faults in the fuzzy logic systolic array can be tolerated by either hardware redundancy or time redundancy. The recomputing with shifted operands (RESO) method, time redundancy, and the triple modular redundancy (TMR) method, hardware redundancy, are applied to fuzzy logic systolic array.

A new transform algorithm for Viterbi decoding

Implementation of the Viterbi decoding algorithm has attracted a great deal of interest in many applications, but the excessive hardware/time consumption caused by the dynamic and backtracking decoding procedures make it difficult to design efficient VLSI circuits for practical applications. A transform algorithm for maximum-likelihood decoding is derived from trellis coding and Viterbi decoding processes. Dynamic trellis search operations are paralleled and well formulated into a set of simple matrix operations referred to as the Viterbi transform (VT). Based on the VT, the excessive memory accesses and complicated data transfer scheme demanded by the trellis search are eliminated. Efficient VLSI array implementations of the VT have been developed. Long constraint length codes can be decoded by combining the processors as the building blocks.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Testing of data paths in VLSI arrays

An important issue in VLSI array design is how to test switches and data links in an array. In the paper, the authors present a ‘divide-and-conquer’ technique for testing data paths in VLSI arrays. The data paths including registers, switches and data links are tested in parallel by applying test patterns from the outside. The fault-free paths identified divide the array into smaller subarrays with fault-free boundaries so that testing can be done recursively. Fault masking due to switch failures is examined. A sufficient condition to avoid fault masking is obtained.

Parallel Computation of the Fast Fourier Transform on a Binary Tree Multiprocessor

AbstractHigh‐speed FFT computation has previously been executed by an array processor using a pipeline processing. However, with advances in VLSI, parallel computation on multiprocessor systems becomes an interesting and challenging problem. In this paper, the parallel FFT computation is performed on a binary tree multiprocessor. The binary tree structure provides a recursive and hierarchical structure, and its processor can be constructed by a simple architecture and embedded efficiently in VLSI array. The binary tree multiprocessor realizes a practical multiprocessor system. First, parallel multidimensional radix 2n FFT algorithms are generalized from the work of Norton and Silberger. Second, to perform efficiently the parallel FFT algorithms, two division and pipeline data communication methods are presented and analyzed. The pipeline method is shown to be powerful.Finally, radix‐2 FFT, radix‐4 FFT, and 2‐D FFT algorithms are implemented on the binary tree machine CORAL68K. High‐performance results are shown. By using various processor capabilities FFT performances are predicted on this machine. Various algorithmic and architectural optimizations on the binary tree machine for the number of data are shown.

Fault detection and design complexity in C-testable VLSI arrays

An extension of a previous approach to fault detection and C-testability of orthogonal iterative arrays is presented. The state transition table of a basic cell is analyzed. Five new states are added to it. It is proved that even though the number of additional states in the proposed approach is greater than previous approaches, (five states compared to four), the required number of test vectors is considerably reduced (by a factor of approximately 4/9). An approach to implement the proposed C-testability approach into logic design is also presented. Complexity of this implementation is analyzed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Nonplanar VLSI arrays with high fault-tolerance capabilities: Shahram Latifi and Ahmed El-Amawy. IEEE Trans. Reliab.38(1), 51 (1989)

Nonplanar VLSI arrays with high fault-tolerance capabilities: Shahram Latifi and Ahmed El-Amawy. IEEE Trans. Reliab.38(1), 51 (1989)

Efficient linear and bilinear arrays for matrix triangularisation with partial pivoting

The paper presents two VLSI arrays for implementing Gaussian elimination with partial pivoting. The first is a bilinear array that uses 2n+1 PEs and triangularises an n*n dense matrix in n/sup 2/+n-2 time units. The second array is a switchable linear array. It uses n PEs to triangularise the n*n dense matrix in 2n/sup 2/-2n+1 time units. Both arrays use strictly local communications and employ simple processing elements (PEs). An optional buffer array can supplement either array to avoid costly inter-iteration I/O. The arrays exhibit an area-time complexity of O(n/sup 3/) which matches the algorithm's time complexity on a uniprocessor. The architectures described are much more efficient than those previously reported by the same authors. >

SYSTOLIC VLSI ARRAY FOR MULTI-VARIABLE FUZZY CONTROL SYSTEMS

Fuzzy logic, based on fuzzy sets theory, incorporates uncertainty and assists in reasoning or decision making processes that are based on incomplete or uncertain information. Fuzzy logic has successfully been employed in expert systems and in rule-based control systems. In this paper, a systolic VLSI array for fuzzy inference computations in multi-variable, multi-input-multi-output, fuzzy control systems is presented. The multi-variable system is decomposed into several multi-input-single-output systems. The designed systolic array consists of several subarray operating, in parallel, on the same inputs. Each subarray represents one multi-input-single-output fuzzy system.

Comment on "Nonplanar VLSI arrays with high fault-tolerance capabilities

In the above-named work (see ibid., vol.38, p.51-7, April 1989), S. Lafiti and A. El-Amawy apply, in a straightforward manner, the method developed by A.D. Singh (1985) to calculate lower bounds for the yield of nonplanar interstitial redundancy topologies of processor arrays with spare processors. In their introduction, they claim that the models suggested by I. Koren and D.K. Pradhan (1987) are highly theoretical since the number of states in the Markov model might be very large and the determination of the transition rates might be intractable. They add that applying some empirical rules, as suggested by Koren and Pradhan (1987), can lead to unrealistic results and may require a large number of computations. They also claim that the model of Koren and Pradhan does not suggest an algorithm to replace faulty elements. They conclude that a simpler model, like the one proposed by Singh, is needed for calculating the yield of fault-tolerant processor arrays. In the present comment, Koren and Pradhan respond to the above comments and attempt to clarify the differences between their yield analysis and that of Singh. >

Parallel processing for supercomputers and artificial intelligence

This book features information on a wide range of key subjects, including vector processors and multi-processors, concurrency control, hypercube systems and key applications, parallel architectures for implementing AI systems, and a comparison of the Cray X-MP-4, the Fujitsu VP-200, and the Hitachi S-810/20. Also explained are such topics as the parallel programming environment and software support, applying AI techniques to program optimization for parallel computers, data flow computations for AI, VLSI array processors for signal/image processing, and optical computing and artificial neural technologies.

Functional testing and verification of array systems

The paper presents a new testing method applicable to VLSI arrays made up of microcomputers as processing elements. A system with single instruction multiple data (SIMD) processing is assumed. In this system, computing elements are connected by a regular interconnection network. A new fault model for the array is presented. Faults are defined at a functional level and allow a systematic test generation procedure to be derived. This procedure is independent of array implementation details and still retains a SIMD characterization. Testing is performed by sequences of instructions. Test sequences are defined by using two ordering criteria. The first criterion establishes the external observability and controllability of the instructions. The second criterion uses instruction cardinality as metric for evaluation of inspection complexity. Algorithms and procedures for a correct execution of functional testing are presented. An example of the application of the proposed technique to an existing parallel scheme made of complex microprocessors is described. The criteria for structuring the test procedure lead to an optimization of fault coverage and a reduction of ambiguity.

Nonplanar VLSI arrays with high fault-tolerance capabilities

VLSI architectures for improved fault tolerance are proposed and analyzed. The architectures include structures with two planar layers of processing elements as well as extended cubic designs. The analyses for arrays with various redundancy levels show remarkable improvement in both array yield and processor use over those exhibited conventional two-dimensional structures. This improvement can be attributed to the benefits of the third dimension to increase the flexibility in spares allocation. The architectures can readily substitute arrays based on mesh or four-nearest-neighbor interconnections. From the fault-tolerance viewpoint the cubic structures offer no appreciable performance improvement over the simpler two-layer structures. >

On mapping algorithms to linear and fault-tolerant systolic arrays

A simple mapping technique is developed to design systolic arrays with limited I/O capability. The technique is used to improve systolic algorithms for some matrix computations on linearly connected arrays of PEs (processor elements) with constant I/O bandwidth. The important features of these designs are modularity with constant hardware in each PE, few control lines, simple data-input/output format, and improved delay time. This technique is extended to design an optimal n square root n-time systolic algorithm for n*n matrix multiplication with O( square root n) I/O bandwidth requirement on a fault-tolerant VLSI model. In this model, the propagation delay is assumed to be proportional to wire length. Fault reconfiguration is achieved by using buffers to bypass faulty PEs, which does not affect the clock rate of the system. The unidirectional flow of control and data assures correctness of the algorithm in the presence of faulty PEs. The design can be implemented on reconfigurable fault-tolerant VLSI arrays using the Diogenes methodology. The present designs are compared to those in the literature and are shown to be superior with respect to I/O format, control, and delay from input to output.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design of algorithm-based fault-tolerant VLSI array processor

In the paper a systematic design methodology which maps a matrix arithmetic algorithm to a fault-tolerant array processor with different topologies and dimensions is presented. The design issues to be addressed in the method are: (a) how to derive a VLSI array with different topologies and dimensions from the algorithm; (b) how to distribute the data processing to the PEs so that a faulty PE will result in limited erroneous data on which the checking scheme is valid. Two examples, matrix multiplication and Givens reduction, are used to illustrate this design method.

Reconfiguration of VLSI arrays by covering

In VLSI arrays, redundant cells are added as spares. The proposed approach is applicable as an offline technique at either production time and/or run time. Reconfiguration is implemented by index mapping using a sequence of two operators. A reconfiguration algorithm which utilizes index mapping is proposed. This algorithm uses a new approach to the assignment problem. It is shown that reconfiguration of fault-free cells is equivalent to a covering of faulty cells by spare cells. It is also established that in a two-dimensional array the optimal spare assignment is given by a maximum matching. This translates to a maximum flow. It is shown that a variation of the matching preserves the optimality of the assignment, while reducing the time complexity of the reconfiguration algorithm Characterization theorems for index mapping and simulation results to substantiate the practicality of the approach are presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Exploitation of parallelism in VLSI array testing

Testing of VLSI/WSI arrays using the spiral testing method is time-consuming due to its sequential nature. In this paper, we propose an efficient testing algorithm which reduces the testing time considerably and requires little hardware overhead. Fault-free data paths are identified first to obtain a high degree of parallelism in cell function unit testing. Cell functional units are then tested by using signature comparisons. Faulty cells determined to be fault-free due to fault masking are removed by subsequent comparisons of responses for every test input. A fairly general fault model is used to cover the faults in the switches and data links as well as the cell functional units.

Residue arithmetic VLSI array architecture for manipulator pseudo-inverse Jacobian computation

The use of residue arithmetic for the exact computation of the manipulator pseudoinverse Jacobian, to obviate the roundoff errors normally associated with the computations, is considered. A two-level macropipelined residue arithmetic array architecture implementing Decell's pseudoinverse algorithm has been developed to overcome the ill-conditioned problem of the pseudoinverse computation. The Decell algorithm is suitable for VLSI array implementation to achieve the real-time computation requirement. The first-level arrays are data-driven, wavefront-like arrays and perform the matrix multiplications, matrix diagonal additions, and trace computations. A pool of the first-level arrays are configured into a second-level macro-pipeline with outputs of one array acting as inputs to another array in the pipe. The proposed architecture can calculate the pseudoinverse Jacobian with a pipelined time in the same computational complexity order as evaluating a matrix product in a wavefront array. >

Minimum-diameter cyclic arrangements in mapping data-flow graphs onto VLSI arrays

Regular arrays of processing elements in VLSI have proved to be suitable for high-speed execution of many matrix operations. To execute an arbitrary computational algorithm on such processing arrays, it has been suggested mapping the given algorithm directly onto a regular array. The computational algorithm is represented by a data-flow graph whose nodes are to be mapped onto processors in the VLSI array.This study examines the complexity of mapping data-flow graphs onto square and hexagonal arrays of processors. We specifically consider the problem of routing data from processors in a given (source) sequence to another (target) sequence.We show that under certain conditions, the above problem is equivalent to the one of finding a minimum-diameter cyclic arrangement. The complexity of the latter problem is analyzed and upper and lower bounds on the number of intermediate rows of processors (between the source and target rows) are derived.

VLSI array processors' block implementation of IIR digital filters

VLSI systolic and wavefront array processors' architectures for the block implementation of infinite impulse response digital filters with very high sample rates are presented. The proposed systolic array processor achieves the maximum possible throughput rate and requires only local data transfers. The asynchronous wavefront array processor operates at the same maximum throughput rate and, moreover, it is characterized by a substantial reduced latency. The throughput rate of the proposed array processor structures is a linear function of the block lengthL and theoretically it may be arbitrary high; however, it is limited only by a number of practical implications.

A low complexity approach for fault detection in C-testable orthogonal VLSI arrays

This paper presents an extension to existing approaches for fault detection and C-testability of orthogonal iterative arrays. C-testability is given by a testing process whose complexity is independent of the dimensions of the arrays and the erroneous states of the cells. The state transition table of a basic cell is analyzed. Five new states are added to it. These states are used to internally reproduce the test input and propagate the faulty state to the output pins of a chip. The testing process is exhaustively analyzed. The characteristics of the additional states are presented. Complexity of the testing process (number of test vectors) is discussed. It is proved that even though the number of additinal states in the proposed approach is greater than previous approaches (five states compared with four), the required number of test vectors is considerably reduced. Illustrative examples are given. An approach to implement the proposed C-testability approach into logic design is also presented. Complexity of this implementation is analyzed. A conjecture about a possible relation between the number of additional states and the complexity of the testing process is postulated.