VLSI Array Research Articles

Efficient VLSI implementation of iterative solutions to sparse linear systems

We propose a novel way of solving systems of linear equations with sparse coefficient matrices using iterative methods on a VLSI array. The nonzero entries of the coefficient matrix are mapped onto a processor array of size √ e × √ e, where e is the number of nonzero elements, n is the number of equations and e ⩾ n. The data transport problem that arises because of this mapping is solved using an efficient routing technique. Preprocessing is carried out on the iteration matrix of the system to compute the routing control-words that are used in the data transfer. This results in O(√ e) time for each iteration of the method, with a small constant factor. As compared to existing VLSI methods for solving the problem, the proposed method yields a superior time performance, greater ease of programmability and an area efficient design. We also develop a second implementation of our algorithm that uses a slightly higher number of communication steps, but reduces the number of arithmetic operations to O(log e). The latter algorithm is suitable for many other architectures as well. The algorithm can be implemented in O(log e) time using e processors on a hypercube, shuffle-exchange, and cube-connected-cycles.

Self-testing approaches for VLSI arrays

A self-testing method which is applicable 1- and 2-dimensional arrays, is presented. The method is based on a state-table-verification approach and a criterion referred to as GI (group identical) testability. GI testability is an extension and modification of PI (partition identical) testability and it is used to simplify response verification for self-testing. It is shown that the response verifier for PI testability does not always detect all faults and a new response verifier for GI-testable arrays is proposed. CGI-testable arrays which are simultaneously C and GI testable, are analysed. It is proved that a C-testable 1-dimensional array with n cells is GI testable if n>or=2T, where T is the least common multiple of the test sequences for verifying a cell in the array. Design for testability approaches for unilateral and bilateral arrays are proposed, and similar conditions are developed for 2-dimensional arrays. Methods for reducing the size of CGI-testable unilateral and bilateral arrays are discussed.

Solving linear systems of equations

The mapping of p-nested loop algorithms into special-purpose VLSI arrays is based on the linear transformations of index sets and data dependence vectors. The problem of synchronizing a sequence of parallel algorithms is also considered. Implementations for complete solving of a linear system of equations with LU decomposition for symmetric positive definite matrices are shown.

The givens-batcher reduction algorithm and matrix triangularisation

A Givens sequence is any sequence of Givens rotations in which zeroes once created are preserved [3]. Givens rotations are applied to a variety of matrix problems, as a means of producing stable non-pivoting triangularisation, and have become popular recently because they are amenable to parallel and VLSI computing. A Batcher sequence is a sequence of comparisons which can be used to sort an arbitrary list of elements in a way that avoids propagation of exchanges by merging pairs of sorted subsequences. In the former case parallelism is admitted because disjoint rotations can be performed in parallel, in the latter the merging can be achieved by nonoverlapping comparisons. Batcher's method produces a highly parallel sorting network suited to VLSI implementation. In this paper we combine the two ideas to produce a Givens-Batcher sequence which reduces a matrix to triangular form using a number of passes. Batchers sorting network can then be employed as a VLSI array with pipelining and high throughput.

A methodology for algorithm regularization and mapping into time-optimal VLSI arrays

This paper provides a fairly comprehensive treatment of a broad class of algorithms as it pertains to systolic implementation. We describe some formal algorithmic transformations that can be utilized to map regular and some irregular compute-bound algorithms into the best-fit time-optimal systolic architectures. This methodology uses the concept of dependence vectors to order in time and space the index points representing the algorithm. However, by differentiating between two types of dependence vectors, the ordering procedure is allowed to be flexible and time optimal. Furthermore, the approach reported here deals with variable as well as fixed dependence vectors and does not put constraints on the topology or dimensionality of the target architecture. The ordered index points are represented by nodes in a diagram called Systolic Precedence Diagram (SPD). The SPD is transformed into a directed graph called the Systolic Directed Graph (SDG) which can be projected along defined directions to obtain the target architectures. If more than one valid projection direction exist, different designs are obtained. The resulting architectures. If more than one valid projection an improvement in the performance can be achieved by increasing PE fan-out. If so, the method provides the corresponding systolic implementation. The methodology has been tried on many signal processing, image processing, and graph theory algorithms and new arrays were designed as a result. In this paper, the methodology is illustrated by mapping three problems, namely, vector-matrix multiplication, matrix-matrix multiplication, and transitive closure problems into many planar and nonplanar time-optimal VLSI arrays.

A RECONFIGURATION TECHNIQUE FOR RELIABLE VLSI DSP ARRAY PROCESSORS

Real-time digital signal processing (DSP) applications require high performance parallel architectures that are also reliable. VLSI arrays are good candidates for providing the required high throughput for these applications. These arrays which consist of a number of regularly interconnected processing elements (PEs) will not function correctly in the presence of even a single fault in any of the PEs. Fault tolerance has therefore become a vital design criterion for VLSI arrays. In this paper, a fault tolerance strategy for VLSI arrays is proposed, which significantly improves the reliability of the system. The fault tolerance scheme is composed of two phases: testing and locating faults (fault detection and diagnosis), and reconfiguration. The first phase employs an on-line error detection technique which achieves a compromise between the space and time redundancy approaches. This concurrent error detection technique reduces the rollback time considerably. The reconfiguration phase is achieved by using a global control responsible for changing the states of the switches in the interconnection network. Backtracking is introduced into the algorithm for maximizing the processor utilization, at the same time keeping the complexity of the interconnection network as simple as possible. Finally, a reliability analysis of this scheme using a Markov model and a comparison with some previous schemes are given.

Systolic VLSI arrays for the metric approach to pattern recognition

This paper presents a VLSI implementation of a parallel algorithm using a diagonal systolic array for on-line pattern recognition. It reveals a natural way of handling large data transfers to the array from the host computer while maximizing the silicon area using a serial approach instead of a standard parallel approach. The important design concerns of expandability and flexibility of the array architecture are discussed.

An associative processing module for a heterogeneous vision architecture

The heterogeneous vision architecture that satisfies the computing demands of real-time computer vision by providing parallelism in three different forms is described. A pipeline of digital signal processing (DSP) chips initially processes signals. Then a SIMD associative processor array processes images and extract features, and a MIMD network of transputers processes extracted objects in parallel. The array's VLSI implementation, the processing modes available due to the use of content-addressable memory, and the means of achieving efficient 2-D interprocessor communication in the linear array are described. An application as a vehicle number plate recognition system is presented. >

Power dissipation of VLSI array processing systems

The Power Factor Approximation (PFA) power estimation method is reviewed and applied to VLSI array processing systems. The power dissipation of 1, 2, and 3 dimensional algorithms implemented on linear, hexagonal, and cubic processor arrays is investigated. Closed form equations are developed which show how the overall power dissipation is influenced by an algorithm's size and dimensionality, the target array processor's size and dimensionality, and the adopted partitioning strategy. The power estimation methods developed in this paper can be applied in the early phases of VLSI algorithm/architecture design, selection, and partitionment. The power dissipation of a matrix-matrix multiplication operation is estimated as an example application.

A hardware implementable two-level parallel computing algorithm for general minimum-time control

A hardware implementable two-level parallel computing algorithm for general minimum-time control is proposed. The minimum-time control problem for a continuous-time system is discretized and transformed into a parameter optimization problem which is large dimensional and nonseparable. The proposed two-level algorithm decomposes this parameter optimization problem into a master-slave problem. The master problem is easily solved by a one-dimensional gradient method, and the slave problem is solved by a parallel computing method which combines recursive quadratic programming with the dual method. The convergence of this iterative two-level parallel computing algorithm under some conditions is proved. On the basis of the VLSI array processor technology, a dedicated hardware computing architecture for realizing this algorithm is presented. The corresponding time complexity, is also analyzed. Simulation of practical problems shows that the algorithm is well suited for real-time application of minimum-time control.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Digit-pipelined on-chip clique-finding VLSI processor for real-time 3-D object recognition

A new on-chip clique-finding VLSI processor is proposed for high-speed graph matching. Using VLSI arrays with the encoded information of all the vertices, the breadth-first search algorithm that finds corresponding vertices between two graphs can be performed in a digital-level pipelining manner. The effect of the digit-pipelined architecture is evaluated. >

On the design of VLSI arrays for discrete Fourier transform

In this paper the design of VLSI arrays for discrete Fourier transform (DFT) is investigated through three topics: (i) algorithm exploitation, derivation and analysis, (ii) array realisation, and (iii) schemes to calculate arbitrarily long length DFT using a reasonable sized array. Four DFT systolic algorithms are examined and compared in terms of computing parallelism and computational complexity. Among the four algorithms, one is newly proposed. The new one exhibits much higher computing parallelism and lower computational complexity than the other three, but is applicable when the DFT length is prime. Based on the four algorithms, seven systolic arrays and seven two-level pipelined systolic arrays are devised. The outstanding features of these arrays are that the number of I/O channels is independent of the DFT length and the time overhead in manipulating consecutive data bundles are eliminated. Two schemes are presented to calculate long-length DFT using arrays with a reasonable number of processing elements. Performance of different algorithms, arrays and schemes is compared and summarised in six tables to serve as the selection criteria for different applications.

A parallel adaptive algorithm for moving target detection and its VLSI array realization

An adaptive innovations-based detection algorithm (IBDA) for moving target detector (MTD) radars is derived. The algorithm behaves well with respect to numerical properties and computational complexity. It possesses high computing parallelism and data locality, making VLSI array realization feasible. A systolic array is designed with an iteration time of (2n+1) and ((n/sup 2/+3n)/2) processing elements, where n is the length of the adaptive filter.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The efficient memory-based VLSI array designs for DFT and DCT

Efficient memory-based VLSI arrays and a new design approach for the discrete Fourier transform (DFT) and discrete cosine transform (DCT) are presented. The DFT and DCT are formulated as cyclic convolution forms and mapped into linear arrays which characterize small numbers of I/O channels and low I/O bandwidth. Since the multipliers consume much hardware area, the designs utilize small ROMs and adders to implement the multiplications. Moreover, the ROM size can be reduced effectively by arranging the data in the designs appropriately. The arrays outperform others in the architectural topology (local and regular connection), computing speeds, hardware complexity, the number of I/O channels, and I/O bandwidth. They benefit from the advantages of both systolic array and the memory-based architectures. >

Comments on "Residue arithmetic VLSI array architecture for manipulator pseudo-inverse Jacobian computation" [with reply

The commenter indicates that in the above-mentioned paper (see ibid., vol.5, no.5, p.569-82 (1989)) the proposed pipelined array architecture for the mixed-radix conversion problem is not as efficient and suitable for VLSI implementation as claimed. The commenter identifies the shortcomings of the design and then gives an efficient systolic/wavefront array that requires fewer hardware resources. The authors reply that this is another valid design for the mixed-radix conversion problem that avoids broadcasting; however, the triangular array of buffers is still required in the design for the data-format conversion, and this problem is not addressed. Since a semisystolic design was not given, the comparison between the original design and the semisystolic design in terms of buffers is premature.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A network flow approach to the reconfiguration of VLSI arrays

A technique for reconfiguring a two-dimensional VLSI array with faulty cells is presented. A network flow model of the problem is used to provide an algorithm for connecting the functional cells of the array so that they simulate a fault-free array of smaller size. The interconnection wires are routed inside horizontal and vertical channels according to the Manhattan model. Experimental results indicate that the algorithm has good performance in practice.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Architectural factors influencing the reliability of fault-tolerant VLSI arrays

Current trend in VLSI technology is toward highly modular structures in which identical Processing Elements (PE) are connected in a regular lattice. Enhancement of the operational reliability of these VLSI devices is obtained by means of fault-tolerance. Fault-tolerance is achieved incorporating spare PE's into the array and designing a flexible interconnection network which is able to support the reconfiguration of the array in the presence of a fault. This paper discusses how architectural related factors influence the configuration and the technology of the device, and how these factors can be accounted for in a predictive reliability model.

FAST IMPLEMENTATION OF MULTIVARIABLE LINEAR SYSTEMS VIA VLSI ARRAY PROCESSORS

The fast implementation of multivariable discrete linear systems via VLSI array processors is presented. Two direct state‐space realizations, the block controller form and the block observer form, are used as the basis for the proposed implementations, which are comprised of similar processing elements in a linear configuration with nearest neighbor links. High concurrency is achieved by exploiting both parallelism and pipelining. The implementations are characterized by modularity, local communication and high throughput rates.

A VLSI array processor for 16-point FFT

An implementation of a two-dimensional array processor for fast Fourier transform (FFT) using a 2- mu m CMOS technology is presented. The array processor, which is dedicated to 16-point FFT, implements a 4*4 mesh array of 16 processing elements (PEs) working in parallel. Design considerations in both the chip level and the PE level are examined. A layout design methodology based on bit-slice units (BSUs) results in a very simple design, easy debugging, and a regular interconnection scheme through abutment. It contains about 48,000 transistors on an area of 53.52 mm/sup 2/, excluding the 83-pad area, and operation is on a 15-MHz clock. The array processor performs 24.6 million complex multiplications per second, and computes a 16-point FFT in 3 mu s.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Fault diagnosis in reconfigurable VLSI and WSI processor arrays

A systematic efficient fault diagnosis method for reconfigurable VLSI/WSI array architectures is presented. The basic idea is to utilize the output data path independence among a subset of processing elements (PEs) based on the topology of the array under test. The "divide and conquer" technique is applied to reduce the complexity of test application and enhance the controllability and observability of a processor array. The array under test is divided into nonoverlapping diagnosis blocks. Those PEs in the same diagnosis block can be diagnosed concurrently. The problem of finding diagnosis blocks is shown equivalent to a generalizedEight Queens problem. Three types of PEs and one type of switches, which are designed to be easily testable and reconfigurable, are used to show how to apply this approach. The main contribution of this paper is an efficient switch and link testing procedure, and a novel PE fault diagnosis approach which can speed up the testing by at leastO(?V?1/2) for the processor arrays considered in this paper, where ?V? is the number of PEs. The significance of our approach is the ability to detect as well as to locate multiple PE, switch, and link faults with little or no hardware overhead.