VLSI array processors' block implementation of IIR digital filters

Abstract

VLSI systolic and wavefront array processors' architectures for the block implementation of infinite impulse response digital filters with very high sample rates are presented. The proposed systolic array processor achieves the maximum possible throughput rate and requires only local data transfers. The asynchronous wavefront array processor operates at the same maximum throughput rate and, moreover, it is characterized by a substantial reduced latency. The throughput rate of the proposed array processor structures is a linear function of the block lengthL and theoretically it may be arbitrary high; however, it is limited only by a number of practical implications.