An efficient multiple shortest augmenting paths algorithm for constructing high performance VLSI subarray

Abstract

Reconfiguring a high-performance subarray of a VLSI array with faults is to construct a maximum target array with the minimum number of long interconnects, which can reduce communication costs, capacitance and dynamic energy dissipation. An existing work proved that the high performance VLSI subarray can be constructed in polynomial time using network flow algorithm. However, because of the disadvantage of the previous network model and the low-performing of standard network flow algorithms for reconfiguration, the efficiency of these algorithms is poor for constructing the high performance VLSI subarray. In this paper, we present an efficient multiple shortest augmenting paths algorithm for rapidly constructing high performance VLSI array. Firstly, we proposed an efficient data structure to construct the network model of the VLSI array with faults, which can dramatically reduce the size of the model compared with previous algorithm. Secondly, a multiple shortest augmenting path algorithm based on the new data structure is proposed, which can significant reduce the running time. Finally, we conduct solid experiments to highlight the efficiency of the proposed method in terms of the running time compared to the standard network flow algorithms. The experimental results show that on a 64 × 64 host array with 0.1% faults, the size of the network model can be reduced by about 50% and the average improvements in running time is up to 85.10% compared with four standard network flow algorithms.