VLSI Array Processors Research Articles

A high-performance VLSI array reconfiguration scheme based on network flow under row and column rerouting

The reconfiguration algorithms have been extensively investigated to ensure the reliability and stability for the processor arrays with faults. It is important to reduce the power consumption, capacitance and communication costs in the processors by reducing the interconnection length of the VLSI array. This paper discusses the reconfiguration problem of the high-performance VLSI processor array under the row and column rerouting constraints. A novel method, making use the idea of network flow, is proposed in this paper. Firstly, a network flow model of the VLSI processor array is constructed, such that the high-performance VLSI target array can be obtained by utilizing the minimal cost flow algorithm. Secondly, we propose a new strategy for bottleneck row selection in the logical array using the minimum cut technique, which can find a more suitable bottleneck row. Finally, we conducted reliable experiments to clearly reveal the efficiency of the new rerouting scheme and algorithm in reducing the number of long interconnects. The experimental results show that, for a host array with size of 256×256, the number of long interconnects in the subarray can be reduced by up to 79.22% and 55.88% without performance penalty for random faults with density of 1% and 25% respectively, when compared with state-of-the-art. In addition, the proposed scheme improves existing algorithm in terms of subarray size. On a 256×256 host array with 25% faulty density, the average improvement in subarray size is up to 3.77% compared with state-of-the-art.

A complete system for NN classification based on a VLSI array processor

This paper describes a VLSI array processor system designed and built for classification problems based on the k-nearest-neighbors approach. This architecture is suitable for different pattern recognition applications and is very efficient for high-dimensional databases. The architecture is scalable with the size of the recognition problem making the system effectively applicable to computational intensive application like on-line pattern recognition. A system prototype composed of a board with two processors, the software driver and a test application have been built and evaluated. For handwritten character recognition task the complete system shows a speed up of 260 times over a sequential algorithm running on a Sun SPARC20 workstation.

Algorithm transformations for the data broadcast elimination method

VLSI technology has had tremendous success in revolutionizing computer design with processor arrays. Local communication and interconnection is a constraint that dictates the design of processor arrays. The shared bus and global access to memory are now no longer used, since they lower the speed. Consequently, parallel algorithms must be designed according to these constraints. One of the problems that must be resolved for the above mentioned constraints is data broadcast elimination. Algorithms must be transformed into a form that uses data propagation instead of data broadcast. Here systems of affine recurrence equations are analyzed and data broadcast is denned in context of the definition of data dependence and affine recurrence equations. A method for data broadcast elimination is introduced in [1] and expands the system of affine recurrence equations into new recurrence equations, that define data propagation and eliminates the data dependences where data broadcast occurs. Parallel algorithms are usually given as a set of similar tasks repetitively performed on different data. The iteration form of presenting the algorithms is most common. Several techniques are introduced to transform the algorithm to a single assignment form of recurrence equations. Some improvements of these techniques are presented to make the application of the data broadcast elimination method easier and more straight forward. The presented techniques are classified as the transformation of iterative algorithms to a recurrence form, the transformation of recurrence form to a single assignment form, and fulfilling the index forms of the algorithms. A system of affine recurrence equations with the data broadcast property is always obtained by applying these procedures. The method of data broadcast elimination successfully transforms this system of affine recurrence equations into a system of uniform recurrence equations which can be used for parallel implementation on VLSI processor arrays.

Localized algorithms for vlsi processor arrays

In this paper we analyze the algorithms expressed as a system of recurrence equations. The algorithms are called 2*1 output algorithms if two output values of one function (variable identification) are specified by the system of recurrence equations for each index point in the algorithm. The algorithm is in free form if the indexes of these two values are not dependent. Two standard classes are determined by this criteria: the nearest neighbour and the all pair form. For example the sorting algorithm can be expressed in the all pair form i.e., the linear insertion algorithm or in the nearest neighbour form i.e., the bubble sort algorithm. However these algorithms are different in their nature. A procedure to eliminate the computational broadcast for the all pair 2*1output algorithm has been proposed by the authors in [1]. The result obtained by implementing this procedure was a localized form of the algorithm and a system of uniform recurrence equations by eliminating the computational and data broadcast. So he data dependence method can be efficiently used for parallel implementations. The proposed procedure cannot be implemented directly on the nearest neighbour form algorithms. Here we show how the algorithm can be restructured into a form where the computational and data broadcast can be eliminated. These transformations result in localized algorithms. A few examples show how these algorithms can be implemented on processor arrays. For example, the Gentleman Kung triangular array [2] can be used for solving the QR decomposition algorithm for both forms of the algorithm. The implementations differ in the order of the data flow and the processor operation. We show that the implementation of the nearest neighbour algorithm is even better than the standard one.

New VLSI array processor design for image window operations

A novel architecture named window-memory sharing processor array is proposed, which targets window operations in image processing. The architecture can be used not only for conventional image filtering, but also in practical window operations such as motion vector search in MPEG2. The derived architecture is flexible enough to satisfy user's requirement for either area or speed.

New Realization and Implementation of Fixed-Point IIR Digital Filters

A new low-roundoff noise realization for narrow-band IIR digital filters with residue feedback and a block triangular system matrix is presented. The block triangular form of the system matrix allows a reduction in the number of arithmetic operations required for the implementation and leads also to a realization which is suitable for high speed implementation. Numerical comparison between the proposed structure and three other low-noise structures shows that the proposed structure provides excellent performance in terms of output roundoff noise and coefficient sensitivity. The output roundoff noise is slightly higher than that of the optimal residue feedback realization proposed by Williamson9 but lower than the optimal realization without residue feedback proposed by Mullis, Roberts and Hwang.6,7 Further an efficient (in terms of speed) VLSI processor array implementation of the proposed IIR structure is also presented. The proposed implementation has been obtained by taking advantage of both the parallel feature of the residue feedback and the block triangular structure of the system matrix of the proposed realization. A hardware comparison between the proposed implementation and another implementation which is based on direct form shows that the proposed implementation provides a higher sampling rate for any narrow-band filter.

Evaluating reliability improvements of fault tolerant array processors using algorithm-based fault tolerance

Algorithm-based fault tolerance (ABFT) is used to provide low-cost error protection for VLSI processor arrays used in real-time digital signal processing. The main objective of incorporating an ABFT technique in a processor array is to improve its reliability. All previous approaches on ABFT are evaluated in terms of their error detecting/correcting capabilities, the reliability improvement has never been addressed. In this paper, we develop a stochastic model for an array processor incorporating ABFT that takes the behavior of transient/intermittent failures and hardware overhead into account. This model is then used to evaluate reliability and reliability improvements of several existing ABFT techniques that tolerate single faults. Therefore, a user can evaluate a number of ABFT techniques and make a trade-off between reliability and cost prior to the implementation. Moreover, we have conducted extensive simulation experiments and the simulation results validate the proposed model.

A VLSI PROCESSOR ARRAY FOR FLEXIBLE STRING MATCHING

This paper presents a systolic design for flexible string matching. Initially a sequential algorithm is discussed which consists of two phases, i.e. pre-processing and searching, and a matrix vector notation of the algorithm is proposed. Then, starting from the computational schedule of the searching phase a systolic algorithm is derived which can be realised directly onto a special purpose VLSI processor array architecture for string matching. Further the pre-processing phase is also accommodated onto the same VLSI design. Finally extensions to approximate pattern matching are discussed.

Algorithm transformations for computational and data broadcast

Problems that must be resolved for the constraints imposed by VLSI technology are computational and data broadcast. Algorithms must be transformed into a form that uses data propagation instead of data broadcast. The techniques introduced here are classified as the transformation of iterative algorithms to a recurrence form, the transformation of recurrence form to a single assignment form, the transformation of the recurrences in iterative algorithms and fulfilling the index forms of the algorithms. Systems of affine recurrence equations are analyzed here and computational and data broadcast are defined in context of the definition of data dependence and affine recurrence equations. A method for data broadcast elimination is introduced in [1, 2] and expands the system of affine recurrence equations into new recurrence equations, that define data propagation and eliminates the data dependencies where computational or data broadcast occurs. Some improvements of these techniques are presented to make the applic ion of the broadcast elimination method easier and more straight forward. A system of affine recurrence equations with broadcast property is always obtained by applying these procedures. The method of broadcast elimination successfully transforms this system of affine recurrence equations into a system of uniform recurrence equations which can be used for parallel implementation on VLSI processor arrays.

Fast Implementation of 3-D Digital Filters Via SystolicArray Processors

In this paper a fast implementation architecture of three-dimensional (3-D) FIR or IIR digital filters via systolic VLSI array processors is described. The modular structure presented is comprised of similar processing elements in a linear cascade configuration with local interconnections. High speed throughput rates are attained due to high concurrency, which is achieved by exploiting both pipelining and parallelism. The considered 3-D FIR and IIR filters may be used for the processing of reconstructed 3-D images and in medical imaging applications.

An efficient dictionary machine using hexagonal processor arrays

Dictionary machine is an important VLSI system performing high speed data archival operations. In this paper, we present a design which can efficiently implement dictionary machines in VLSI processor arrays. In order to effectively process the operations of dictionary machine, hexagonal mesh is selected as the host topology in which two different networks for update and query operation are embedded. The proposed design is simple to implement as well as allows high throughput.

Functionally asynchronous array processor for morphological filtering of greyscale images

The design of a fine-grain asynchronous VLSI array processor is presented. It demonstrates how asynchronism can be exploited both at functional and architectural levels. A joint algorithm–architecture study that has resulted in the design of a 16 × 16 processor array is described, and the design flow used to implement both data-paths and control parts is presented. This is based on a standard cell approach that combines differential cascode voltage switch logic blocks and standard CMOS gates. The chip has been fabricated using the CNET/SGS-Thomson 0.5 µm CMOS triple metal layer technology, including 800 000 transistors in an area of 8 × 9 mm2. This allows real-time iterative morphological filtering of greyscale 256 × 256 pixels images at ~40 Hz frame rate.

Pipeline interleaving design for FIR, IIR, and FFT array processors

In this paper, a floating point multiply- and-accumulate (FMAC) processor capable of running the FIR, IIR, and FFT algorithms is proposed. This processor executes many independent FMAC operations circularly without causing any hazard. The algorithmic processing is decomposed into independent subprocesses, each of which executes a FMAC group and all of the subprocesses are activated in turn. The projection method of VLSI array processors is used to map the data flow of FIR, IIR, and FFT into subprocesses so that the algorithms can be successfully executed by the processor in the way of pipeline interleaving. Because of the 100% utilization of pipeline, a very good performance is achieved.

A COST-EFFECTIVE STREAMLINING OF THE DIOGENES DESIGN METHODOLOGY

The original DIOGENES design methodology produces fault-tolerant layouts of VLSI processor arrays by designing an array's interconnection network as a (possibly large) number of (re)configurable bundles of wires, each bundle being organized as either a stack or a queue. The benefits of DIOGENES often come only at high cost, in terms of both configuration hardware and algorithmic cost of configuration. In this paper, we improve the original methodology in a way that simultaneously: streamlines the design process; produces more cost-effective layouts; can be augmented to allow efficient dynamic reconfigurability. Our new version of DIOGENES replaces the wire-stacks and/or -queues of the original methodology by a single generalized deletion stack (GDS for short), independent of the topology of the array. The new methodology has three major benefits: 1. A GDS-network can be configured in time linear in the size of the graph being realized. (Optimal network configuration is superlinear for the queue-based version and NPcomplete for the stack-based version of the original methodology.) 2. A GDS-network can realize any linearization of any graph, subject only to the constraints of the implemented node-degree and cutwidth. (The original methodology demands a priori commitment to a fixed number of stacks or queues of fixed sizes, hence limits one to a restricted set of array topologies.) 3. A GDS-network usually requires dramatically less configuration hardware than a stack- or queue-based network would (albeit with larger switches). We end with suggested enhancements to this new, flexible, version of DIOGENES.

Architecture and Operations of the VLSI Array Processors for Implementing a Receding Horizon Controller

In this paper, we present the architecture of VLSI array processors for implementing a receding horizon controller which is designed for constrained nonlinear systems based on a two-phase parallel computing algorithm. We also describe the operations of these VLSI array processors and present the arithmetic operations and control logic required in each processing element. On the basis of current VLSI technology, the estimated computing time of obtaining the receding horizon feedback control solution meets the real-time processing system needs.

VLSI array processors for linear-phase FIR filters

Array processor implementations are obtained for linear-phase FIR filters. Three structures are reported in which the inputs are pipelined and/or broadcast and the outputs are pipelined. A novel structure is obtained in which the outputs are localized in separate processing elements. A comparison among the resulting structures is performed based on the processing rate, the latency, and the communication overhead perspectives. A new fixed-point array-multiplier design is then presented. The new processor can perform an add-multiply-accumulate operation in the same time as a simple multiplier. It increases the speed of operation without incurring extra silicon area or introducing extra latency to the system.

Implementation of matrix decomposition structures of 2-D digital filters via VLSI array processors

This paper describes an implementation of 2-D FIR and IIR linear digital filters via VLSI array processors. The underlying realization structures are based on the matrix decomposition approach. The 2-D concurrent processing is used in order to implement the row and column delays within the cycle time. A high degree of concurrency is achieved by exploiting the pipelining of the array processors with the inherent parallelism of the matrix decomposition structure. The resulting structures are modular, and regular, use only local communication and internal local feedback loops, and achieve high throughput and sampling rates.

Parallel modeling and structure of nonlinear Volterra discrete systems

A parallel modeling of the nonlinear finite extent Volterra discrete systems, which exploits the inherent symmetries and ensures fast implementation and design with the minimum computational and hardware cost, is presented. The parallel realization model is based on the successive decomposition of the kth order Volterra kernel in terms of lower order kernels, which are ordered in sequential nested subkernels. The resulting parallel realization is a tree structure with inputs the associated quadratic Volterra kernels. Each layer of the tree structure is comprised of nodes that represent the kernels of the same order and can be computed independently and simultaneously. The proposed parallel model is characterized by a great degree of modularity and regularity, since it uses only planar triangular arrays and local communications, and constitutes the basis for efficient fast implementations using VLSI array processors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A VLSI processor array for graph isomorphism

Complex images represented through relational graphs can be recognized finding the isomorphic graph in a database of stored images. In this paper, the basic node of a processor array able promptly to verify the graph isomorphism is described. The internal architecture has been tuned on the algorithm behaviour and a first prototype containing four processors has been realized in the frame of the Eurochip program, using ES2 1-5 urn technology, while a successive version in ST 0-8 urn technology is currently being developed.

A hardware implementable receding horizon controller for constrained nonlinear systems

We present a two-phase parallel computing method for obtaining an implementable receding horizon control solution for constrained nonlinear systems. The phase 1 method solves a feasibility problem to find an approximate open-loop admissible control and horizon pair. The phase 2 method successively improves the admissible control to obtain an implementable open-loop receding horizon control solution. We briefly sketch an approach to realizing this two-phase method using VLSI array processors. Solution times for simulation examples estimated on the basis of current VLSI technology confirm that our controller is well suited to the stabilization of real-time processing, fast, constrained nonlinear systems. >