A VLSI PROCESSOR ARRAY FOR FLEXIBLE STRING MATCHING

Abstract

This paper presents a systolic design for flexible string matching. Initially a sequential algorithm is discussed which consists of two phases, i.e. pre-processing and searching, and a matrix vector notation of the algorithm is proposed. Then, starting from the computational schedule of the searching phase a systolic algorithm is derived which can be realised directly onto a special purpose VLSI processor array architecture for string matching. Further the pre-processing phase is also accommodated onto the same VLSI design. Finally extensions to approximate pattern matching are discussed.