A COST-EFFECTIVE STREAMLINING OF THE DIOGENES DESIGN METHODOLOGY

Abstract

The original DIOGENES design methodology produces fault-tolerant layouts of VLSI processor arrays by designing an array's interconnection network as a (possibly large) number of (re)configurable bundles of wires, each bundle being organized as either a stack or a queue. The benefits of DIOGENES often come only at high cost, in terms of both configuration hardware and algorithmic cost of configuration. In this paper, we improve the original methodology in a way that simultaneously: streamlines the design process; produces more cost-effective layouts; can be augmented to allow efficient dynamic reconfigurability. Our new version of DIOGENES replaces the wire-stacks and/or -queues of the original methodology by a single generalized deletion stack (GDS for short), independent of the topology of the array. The new methodology has three major benefits: 1. A GDS-network can be configured in time linear in the size of the graph being realized. (Optimal network configuration is superlinear for the queue-based version and NPcomplete for the stack-based version of the original methodology.) 2. A GDS-network can realize any linearization of any graph, subject only to the constraints of the implemented node-degree and cutwidth. (The original methodology demands a priori commitment to a fixed number of stacks or queues of fixed sizes, hence limits one to a restricted set of array topologies.) 3. A GDS-network usually requires dramatically less configuration hardware than a stack- or queue-based network would (albeit with larger switches). We end with suggested enhancements to this new, flexible, version of DIOGENES.