Functionally asynchronous array processor for morphological filtering of greyscale images

Abstract

The design of a fine-grain asynchronous VLSI array processor is presented. It demonstrates how asynchronism can be exploited both at functional and architectural levels. A joint algorithm–architecture study that has resulted in the design of a 16 × 16 processor array is described, and the design flow used to implement both data-paths and control parts is presented. This is based on a standard cell approach that combines differential cascode voltage switch logic blocks and standard CMOS gates. The chip has been fabricated using the CNET/SGS-Thomson 0.5 µm CMOS triple metal layer technology, including 800 000 transistors in an area of 8 × 9 mm2. This allows real-time iterative morphological filtering of greyscale 256 × 256 pixels images at ~40 Hz frame rate.