Architecture and Operations of the VLSI Array Processors for Implementing a Receding Horizon Controller

Abstract

In this paper, we present the architecture of VLSI array processors for implementing a receding horizon controller which is designed for constrained nonlinear systems based on a two-phase parallel computing algorithm. We also describe the operations of these VLSI array processors and present the arithmetic operations and control logic required in each processing element. On the basis of current VLSI technology, the estimated computing time of obtaining the receding horizon feedback control solution meets the real-time processing system needs.