Design of fine grain VLSI array processor for real-time 2D digital filtering

Abstract

Fine grain VLSI array processors for real-time 2-D state-space digital filters are designed and evaluated. The architecture of the VLSI array processors is a linear systolic array, of which processing elements (PEs) are simple and homogeneous 1-D state-space digital filters. The number of PEs is equal to the number of rows of the processing images. A hierarchical behavioral description language and a synthesizer are utilized for the design and evaluation of the VLSI array processors. One VLSI chip is composed of 129 k gates and is integrated into one 14.70 /spl times/ 14.98 mm/sup 2/ VLSI chip using 1-/spl mu/m CMOS technology. Eight PEs can be integrated into one VLSI chip. The fine grain VLSI chips at 25 MHz clock can process a 1,024 /spl times/ 1,024 image in 1.47 msec, and can be applied to real-time video signal processing. >