Virtex-5 Field Programmable Gate Array Research Articles

RDCSAE-RKRVFLN: A unified deep learning framework for robust and accurate DOA estimation

This paper introduces an innovative unified deep learning (DL) model, “reduced deep convolutional stack autoencoder (RDCSAE)-robust kernel-based random vector functional link network (RKRVFLN)” (RDCSAE-RKRVFLN), for addressing practical challenges like phase and gain uncertainty, mutual coupling effects, and element position errors in direction of arrival (DOA) estimation. The RDCSAE utilizes deep convolutional neural network (DCNN) and stack autoencoder (SAE) for robust feature extraction. The RKRVFLN integrates a concise SAE output with kernel-based learning. Thus, the integration of RDCSAE (suitable for unsupervised feature extraction) and RKRVFLN (for supervised learning) in the developed model results in efficient use of limited training data. Performance metrics of this method include among others the accuracy (separation between sources), root mean square error (RMSE), signal-to-noise ratio (SNR), etc. The method performs better than existing data driven methods in terms of computational efficiency, faster learning speed, enhanced model generalization, higher accuracy, and shorter event regression time and empirical methods. In the presence of above mentioned four perturbations, this method successfully resolves multiple sources with a resolution of 0.3° with a RMSE of 0.00376. For real time application, the paper implements RDCSAE-RKRVFLN on a high-speed reconfigurable Xilinx Virtex-5 field-programmable gate array (FPGA) realizing a digital DOA estimator for one source. The hardware estimates the DOA with a maximum error of 0.01953125 which follows closely the simulation results indicating the efficiency and feasibility of the method.

Resource-aware Montgomery modular multiplication optimization for digital signal processing

Homomorphic encryption is an important technology for protecting data privacy, and the performance of modular multiplication directly affects the efficiency of homomorphic encryption. Currently, there are numerous FPGA-based acceleration techniques targeting modular multiplication. However, many of these implementations require substantial hardware resources or suffer from resource imbalance. This leads to a lower throughput. Therefore, we present a novel FPGA-based implementation of Montgomery Modular Multiplication aimed at addressing these challenges. Our design employs a suitable radix bit width and word size based on the digital signal processing (DSP) bit width rather than the conventional binary powers of two. We aim to instantiate more modular multipliers using limited resources while minimizing latency. We also introduce a novel DSP cascade structure, called parallel grouping cascade DSP, which reduces the number of clock cycles of internal multipliers. To balance the ratio of lookup table (LUT) and DSP usage, we also use multipliers implemented in the LUT to replace some DSPs. Our results, implemented on Xilinx Virtex-7 field-programmable gate array (FPGA), demonstrate more than 27% improvement in throughput on 1024-bit modular multiplication and more than 70% improvement on 2048-bit compared to the best previous state-of-the-art references.

A Flexible Hardware Accelerator for Booth Polynomial Multiplier

This article presents a parameterized/flexible hardware accelerator design tailored for the Booth polynomial multiplication method. The flexibility is achieved by allowing users to compute multiplication operations across various operand lengths, reaching up to 212 or 4096 bits. Our optimization strategy involves resource reuse, effectively minimizing the overall area cost of the Booth accelerator design. A comprehensive evaluation compares the proposed multiplier design with several non-digitized bit-serial polynomial multiplication accelerators. Implementation is realized in Verilog HDL using the Vivado IDE tool, featuring diverse operand sizes, and post-place and route assessments are performed on the Xilinx Virtex-7 field-programmable gate array device. For the largest considered operand size of 1024 × 1024, our Booth accelerator utilizes 1434 slices and can operate on a maximum frequency of 523.56 MHz. A single polynomial multiplication operation requires 0.977 μs and the total power consumption is 927 mW. Moreover, a comparison to state-of-the-art accelerators reveals that the proposed flexible accelerator is 1.34× faster in computation time and 1.05× more area-efficient than the recent dedicated polynomial multiplication design. Therefore, the implementation results and comparison to the state of the art show that the proposed accelerator is suitable for a wide range of cryptographic applications.

A reduced complexity rate-matching and channel interleaver/de-interleaver for 5G NR

Rate matching and channel interleavers play a pivotal role in code rate adaptation and minimizing burst errors in communication systems. The data and control channels in the Fifth generation (5G) New Radio (NR) employs distinct channel interleavers/de-interleavers for reducing bit error rate. However, the independent implementation results in a substantial increase in silicon cost. To address this challenge, hardware sharing is pivotal for optimizing resource utilization and improving overall system performance. This study introduces a rate-matching architecture and a simple algorithm for the creation of a new Shared-Resource Channel interleaver/De-interleaver (SRC) architecture. The proposed work ensures low complexity tailored for both data and control channels within the 5G NR framework by incorporating the hardware sharing technique. The proposed SRC architecture, synthesized on the Virtex-7 Field Programmable Gate Array (FPGA), showcases noteworthy advancements over existing 5G NR interleaver architecture, achieving a notable 23% reduction in resource utilization. Through implementation using the Qflow Compiler in 45 nm CMOS technology, the ASIC synthesis of the proposed design demonstrates a substantial decrease in hardware complexity and area by 44.6% and 43%, respectively. Furthermore, the proposed architecture exhibits a 19.2% reduction in power consumption compared to its existing counterpart in 5G NR. The proposed integrated design demonstrates a remarkable resource efficiency by occupying nearly half the resources compared to individual implementations.

FPGA implementation of DTCWT architecture's high-speed DA structure for OFDM-based transceiver with CS

Communication systems at millimeter-wave (mm-wave) frequencies with high propagation losses use radio frequency (RF) budget analysis. RF system gains and losses ensure the receiver can recover the broadcast signal. Modern communication systems use compressive sensing (CS) and discrete wavelet transform (DWT). Hardware implementation is hard. Fieldprogrammable gate arrays (FPGA) adaptability, configurability, and processing speed make them popular. More mm-wave transceivers use FPGAs and advanced signal processing. FPGA-based mm-wave transceivers use compressed sensing and dual-tree complex wavelet transform (DTCWT). RF budget analysis recovers receiver signals. Energy and data efficiency transceivers have baseband processors, transmitters, and receivers. RF-to-mm-wave transmitter. Receiver demodulation and baseband conversion. CS and DTCWT processing modules boost baseband signal processing 5 Gbps Xilinx virtex-6 FPGAs. The system retrieves the signal while conserving power, according to simulations and testing. This study found that FPGA-based mm-wave transceivers can use advanced signal processing in future high-speed communication systems.

A novel digital intermediate frequency module for hyperspectral microwave radiometers based on the parallel fast Fourier transform algorithm.

Microwave radiometers, possessing all-day and all-weather operational capabilities, are extensively utilized in the exploration of planetary atmospheres and surfaces. The potential of the hyperspectral detection technology to enhance the precision and resolution of microwave radiometer detection has made it a crucial research focus. This paper introduces an intermediate frequency (IF) module for hyperspectral microwave radiometers. The IF module is constructed with two 6.4 gigabit samples per second sampling-rate analog-to-digital converter (ADC) chips and a Xilinx Virtex-7 field programmable gate array. By implementing a parallel fast Fourier transform algorithm and a pipeline architecture, the IF module can efficiently process all ADC sampling data in real-time, generating 512 channels of output for each ADC. The test results, including linearity, sensitivity, and flatness, are presented and thoroughly analyzed for the IF module. Furthermore, the module is interfaced with the radio frequency front-end of the microwave radiometer to measure hot and cold calibration sources and assess its sensitivity. When combined with a suitable front-end receiver, the IF module can form a radiometer system suitable for various applications of microwave remote sensing.

Sequential logic circuit gold codes for electronics and communication technologies

The linear feedback shift register (LFSR) and Gold codes are used in telecommunications, Global Positioning System (GPS), satellite navigation, wireless systems, and code division multiple access (CDMA) dependent channel schemes for numerous radio communication technologies Gold codes are distinguished by their capacity to provide various orthogonal sequences.•The objective of the article is to focus on the design and simulation of the LFSR-based gold code generator chip in Xilinx ISE 14.7 software with the logic synthesis in Virtex-5 field programmable gate array (FPGA) and check the switching behavior with large frequency support applicable in fast-switching optical, and wireless electronics systems.•The methodology comprises design, functional simulation with different test inputs, and FPGA synthesis. The chip design is verified for the 10-bit seeding sequence of LFSRs to result in 1023-bit code with the frequency support of 310 MHz, and 9.285 ns delay.•The chip design is simulated based on seed data and different tap points of LFSR registers from which the bits are considered to generate the feedback. The design is scalable and has greater potential to extend to a larger extent. The behavior of the gold code depends on the maximum length sequence, absolute cross-correlation, and size of LFSR.

FPGA-based remote target classification in hyperspectral imaging using multi-graph neural network

Hyperspectral imagery (HSI) is widely used in remote sensing for target classification; however, its accurate classification remains challenging due to the scarcity of labeled data. Graph Neural Networks (GNNs) have emerged as a popular method for semi-supervised classification, attracting significant interest in the context of HSI analysis. Nevertheless, conventional GNN-based approaches often rely on a single graph filter to extract HSI characteristics, failing to fully exploit the potential benefits of different graph filters. Additionally, oversmoothing issues plague classical GNNs, further affecting classification performance. To address these drawbacks, we propose a novel approach called Spectral and Autoregressive Moving Average Graph Filter for the Multi-Graph Neural Network (SAM-GNN). This approach leverages two distinct graph filters: one specialized in extracting the spectral characteristics of nodes and the other effectively suppressing graph distortion. Through extensive evaluations, we compare the performance of SAM-GNN with other state-of-the-art methods, employing metrics such as overall accuracy (OA), individual class accuracy (IA), and Kappa coefficient (KC). The results shows that the SAM-GNN provides an improvement in KC, IA, and OA of 6.71%, 5.7%, and 3.93% for the Pavia University dataset and 4.67%, 3.67%, and 3.49% for the Cuprite dataset respectively. Furthermore, we implement SAM-GNN on the Virtex-7 field-programmable gate array (FPGA), demonstrating that the method achieves highly accurate target localization results, bringing us closer to real-world applications in HSI classification.

Fuzzy current analysis-based fault diagnostic of induction motor using hardware co-simulation with field programmable gate array

Introduction. Presently, signal analysis of stator current of induction motor has become a popular technique to assess the health state of asynchronous motor in order to avoid failures. The classical implementations of failure detection algorithms for rotating machines, based on microprogrammed sequential systems such as microprocessors and digital signal processing have shown their limitations in terms of speed and real time constraints, which requires the use of new technologies providing more efficient diagnostics such as application specific integrated circuit or field programmable gate array (FPGA). The purpose of this work is to study the contribution of the implementation of fuzzy logic on FPGA programmable logic circuits in the diagnosis of asynchronous machine failures for a phase unbalance and a missing phase faults cases. Methodology. In this work, we propose hardware architecture on FPGA of a failure detection algorithm for asynchronous machine based on fuzzy logic and motor current signal analysis by taking the RMS signal of stator current as a fault indicator signal. Results. The validation of the proposed architecture was carried out by a co-simulation hardware process between the ML402 boards equipped with a Virtex-4 FPGA circuit of the Xilinx type and Xilinx system generator under MATLAB/Simulink. Originality. The present work combined the performance of fuzzy logic techniques, the simplicity of stator current signal analysis algorithms and the execution power of ML402 FPGA board, for the fault diagnosis of induction machine achieving the best ratios speed/performance and simplicity/performance. Practical value. The emergence of this method has improved the performance of fault detection for asynchronous machine, especially in terms of hardware resource consumption, real-time online detection and speed of detection.

An Optimized Flexible Accelerator for Elliptic Curve Point Multiplication over NIST Binary Fields

This article proposes a flexible hardware accelerator optimized from a throughput and area point of view for the computationally intensive part of elliptic curve cryptography. The target binary fields, defined by the National Institute of Standards and Technology, are GF(2163), GF(2233), GF(2283), GF(2409), and GF(2571). For the optimization of throughput, the proposed accelerator employs a digit-parallel multiplier. The size of the digit is 41 bits. The proposed accelerator has reused the multiplication and squaring circuit for area optimization to compute modular inversions. Flexibility is included using three additional buffers on top of the proposed accelerator architecture to load different input parameters. Finally, a dedicated controller is used to optimize control signal handling. The architecture is modeled using Verilog and implemented up to the post-place-and-route level on a Xilinx Virtex-7 field-programmable gate array. The area utilization of our accelerator in slices is 1479, 1998, 2573, 3271, and 4469 for m=163 to 571. The time needed to perform one-point multiplication is 7.15, 10.60, 13.26, 20.96, and 30.42 μs. Similarly, the throughput over area figures for the same key lengths are 94.56, 47.21, 29.30, 14.58, and 7.35. Consequently, achieved results and a comprehensive performance comparison show the suitability of the proposed design for constrained environments that demand throughput/area-efficient implementations.

An efficient design methodology to speed up the FPGA implementation of artificial neural networks

In this paper, we propose and formulate a C++ based training methodology for speeding up the implementation of an Artificial Neural Network (ANN) in a Field Programmable Gate Array (FPGA). The proposed ANN implementation methodology uses a custom C++ based program referred to as Neural Network Design Parameter Extraction (NNDPE) program developed using an open source library namely Fast Artificial Neural Network (FANN). The proposed C++ based NNDPE program reduces the time required to train and extract the design parameters of the ANN, such as the number of layers, the number of neurons in each layer, and the weights. The extracted ANN design parameters, custom hardware arithmetic units, and function-approximate activation functions are used to implement the ANN hardware architecture of a linear function on the Virtex-7 FPGA platform. The Vivado 2018.3 tool is used to simulate, synthesize, and implement the ANN-based linear function. It was concluded from the simulation that the ANN hardware implementation has high precision due to the usage of floating-point arithmetic operations compared to the ANN which uses fixed-point arithmetic operations. The ANN-implemented on the Virtex-7 FPGA operates at 150.76 MHz, which is approximately 11 to 18 times faster than the software implementation running on various CPU cores with operating frequencies ranging over 2.2 GHz to 4.70 GHz.

Throughput/Area-Efficient Accelerator of Elliptic Curve Point Multiplication over GF(2233) on FPGA

This paper presents a throughput/area-efficient hardware accelerator architecture for elliptic curve point multiplication (ECPM) computation over GF(2233). The throughput of the proposed accelerator design is optimized by reducing the total clock cycles using a bit-parallel Karatsuba modular multiplier. We employ two techniques to minimize the hardware resources: (i) a consolidated arithmetic unit where we combine a single modular adder, multiplier, and square block instead of having multiple modular operators, and (ii) an Itoh–Tsujii inversion algorithm by leveraging the existing hardware resources of the multiplier and square units for multiplicative inverse computation. An efficient finite-state-machine (FSM) controller is implemented to facilitate control functionalities. To evaluate and compare the results of the proposed accelerator architecture against state-of-the-art solutions, a figure-of-merit (FoM) metric in terms of throughput/area is defined. The implementation results after post-place-and-route simulation are reported for reconfigurable field-programmable gate array (FPGA) devices. Particular to Virtex-7 FPGA, the accelerator utilizes 3584 slices, needs 7208 clock cycles, operates on a maximum frequency of 350 MHz, computes one ECPM operation in 20.59 μs, and the calculated value of FoM is 13.54. Consequently, the results and comparisons reveal that our accelerator suits applications that demand throughput and area-optimized ECPM implementations.

Hardware architecture design for complementary ensemble empirical mode decomposition algorithm

In this paper, we have presented a field-programmable gate array (FPGA) as well as an application-specific integrated circuit (ASIC) based design for the complementary ensemble empirical mode decomposition (CEEMD) algorithm. CEEMD is an adaptive signal analysis method that decomposes an input signal into many signals, each of which is termed an intrinsic mode function (IMF). In this work, the CEEMD architecture is developed in the form of Verilog-HDL code. The ASIC is designed by using a 180 nm technology library. Our proposed ASIC can be operated at a clock rate of 58.82 MHz, and the total power dissipation of the ASIC is 76.20 mW. The core area of the CEEMD ASIC is 1.53 mm2. The FPGA-based design of CEEMD can work with a clock rate of 50 MHz, and Virtex-7 FPGA is used for the implementation purpose. The proposed parallel architecture of CEEMD extensively reduces the computational time of the design by employing parallel processing. FPGA and the ASIC-based design of CEEMD have very less computation time and can be used for real-time applications.

A Unified Point Multiplication Architecture of Weierstrass, Edward and Huff Elliptic Curves on FPGA

This article presents an area-aware unified hardware accelerator of Weierstrass, Edward, and Huff curves over GF(2233) for the point multiplication step in elliptic curve cryptography (ECC). The target implementation platform is a field-programmable gate array (FPGA). In order to explore the design space between processing time and various protection levels, this work employs two different point multiplication algorithms. The first is the Montgomery point multiplication algorithm for the Weierstrass and Edward curves. The second is the Double and Add algorithm for the Binary Huff curve. The area complexity is reduced by efficiently replacing storage elements that result in a 1.93 times decrease in the size of the memory needed. An efficient Karatsuba modular multiplier hardware accelerator is implemented to compute polynomial multiplications. We utilized the square arithmetic unit after the Karatsuba multiplier to execute the quad-block variant of a modular inversion, which preserves lower hardware resources and also reduces clock cycles. Finally, to support three different curves, an efficient controller is implemented. Our unified architecture can operate at a maximum of 294 MHz and utilizes 7423 slices on Virtex-7 FPGA. It takes less computation time than most recent state-of-the-art implementations. Thus, combining different security curves (Weierstrass, Edward, and Huff) in a single design is practical for applications that demand different reliability/security levels.

Performance analysis of multiple input single layer neural network hardware chip.

An artificial neural network (ANN) is a computational system that is designed to replicate and process the behavior of the human brain using neuron nodes. ANNs are made up of thousands of processing neurons with input and output modules that self-learn and compute data to offer the best results. The hardware realization of the massive neuron system is a difficult task. The research article emphasizes the design and realization of multiple input perceptron chips in Xilinx integrated system environment (ISE) 14.7 software. The proposed single-layer ANN architecture is scalable and accepts variable 64 inputs. The design is distributed in eight parallel blocks of ANN in which one block consists of eight neurons. The performance of the chip is analyzed based on the hardware utilization, memory, combinational delay, and different processing elements with targeted hardware Virtex-5 field-programmable gate array (FPGA). The chip simulation is performed in Modelsim 10.0 software. Artificial intelligence has a wide range of applications, and cutting-edge computing technology has a vast market. Hardware processors that are fast, affordable, and suited for ANN applications and accelerators are being developed by the industries. The novelty of the work is that it provides a parallel and scalable design platform on FPGA for fast switching, which is the current need in the forthcoming neuromorphic hardware.

VLSI Architecture of DCT-Based Harmonic Wavelet Transform for Time–Frequency Analysis

The complex harmonic wavelet(CHW) is being used to directly compute frequency content with respect to time by employing discrete Fourier transform(DFT) and inverse discrete Fourier transform. However, DFT coefficients suffer severe leakage of energy from one band to another band of frequency. The leakage between bands is minimized by employing discrete cosine transform(DCT) in the harmonic wavelet transform, which leads to a better representation of the time-frequency spectrum. This paper introduces a new VLSI architecture for DCT-based harmonic wavelet for hardware implementation and prototyped on a commercially available virtex5 field-programmable gate array(xc5vlx110t). To validate the proposed implementation, its real-time captured results in the logic analyzer are verified with simulation results. The maximum operating frequency targeting the FPGA mentioned above device is reported as 114.34 MHz. The total On-Chip power of the above implementation is 1.102W, out of which 68mW is the dynamic power dissipation at a toggle rate of 12%. Finally, for the area utilization of the above implementation, its resource utilization targeting the above FPGA device is reported.

A Coprocessor Architecture for 80/112-bit Security Related Applications

We have proposed a flexible coprocessor key-authentication architecture for 80/112-bit security-related applications over field by employing Elliptic-curve Diffie Hellman (ECDH) protocol. Towards flexibility, a serial input/output interface is used to load/produce secret, public, and shared keys sequentially. Moreover, to reduce the hardware resources and to achieve a reasonable time for cryptographic computations, we have proposed a finite field digit-serial multiplier architecture using combined shift and accumulate techniques. Furthermore, two finite-state-machine controllers are used to perform efficient control functionalities. The proposed coprocessor architecture over and is programmed using Verilog and then implemented on Xilinx Virtex-7 FPGA (field-programmable-gate-array) device. For and , the proposed flexible coprocessor use 1351 and 1789 slices, the achieved clock frequency is 250 and 235 MHz, time for one public key computation is 40.50 and 79.20 μs and time for one shared key generation is 81.00 and 158.40 μs. Similarly, the consumed power over and is 0.91 and 1.37 mW, respectively. The proposed coprocessor architecture outperforms state-of-the-art ECDH designs in terms of hardware resources.

FPGA-Based Implementation of Multidimensional Reconciliation Encoding in Quantum Key Distribution

We propose a multidimensional reconciliation encoding algorithm based on a field-programmable gate array (FPGA) with variable data throughput that enables quantum key distribution (QKD) systems to be adapted to different throughput requirements. Using the circulatory structure, data flow in the most complex pipeline operation in the same time interval, which enables the structural multiplexing of the algorithm. We handle the calculation and storage of eight-dimensional matrices cleverly to conserve resources and increase data processing speed. In order to obtain the syndrome more efficiently, we designed a simplified algorithm according to the characteristics of the FPGA and parity-check matrix, which omits the unnecessary operation of matrix multiplication. The simplified algorithm could adapt to different rates. We validated the feasibility and high speed of the algorithm by implementing the multidimensional reconciliation encoding algorithm on a Xilinx Virtex-7 FPGA. Our simulation results show that the maximum throughput could reach 4.88 M symbols/s.

Programmable implementation of time-area-efficient Elliptic Curve Cryptography for entity authentication

In the ever increasing wireless reliant technologies, communications and devices, the demand for effective security with low hardware and high speed is wanting in the cryptography domain. Among the various cryptographic algorithms, the Elliptic Curve Cryptography (ECC) provides an attractive solution for this demand. In this paper, the Remote Keyless system Authentication process using the ECC has been implemented in Field Programmable Gate Array (FPGA). The designed ECC processor supports 256-bit point multiplication and point addition on the Koblitz curve secp256k1. The scalar multiplication has been performed with the faster multiplier Urdhva Tiryagbhyam. Additionally, pipelining has been incorporated in order to speed up the multiplication process of the processor. The proposed ECC processor performs single point multiplication of 256-bit in 1.2062ms with a maximum clock frequency of 192.5MHz, which provides 212.23kbps throughput and occupies 8.23k slices in Virtex-7 FPGA. Incorporating pipeline in scalar multiplication improves the maximum clock frequency up to 15.12%, reduces time consumption by 22.36%, which in turn increases the throughput by 22.36%. The proposed pipelined Vedic multiplier based ECC processor outperforms the existing designs in terms of area, operating frequency, area-delay product and throughput. Hence, the implementation of the proposed method offers time-area-efficient fast scalar multiplication with effective hardware utilization without any compromise in security level.

Hardware Implementation of a High Efficiency and High-Speed Squaring Architecture

This paper presents the design of a high speed and simple squaring structure based on half adder and full adder. The proposed architecture consists of three main steps; simplification of the squaring structure, calculation and transferring of the carry bit to the next part, and finally, applying the modified Wallace Tree Adder to calculate the summation of the products. The proposed squaring architecture is formed only by 13 half adders and 20 full adders for 8-bit squaring which has the lowest complexity compared to other works. The proposed structure is modeled by using Field-Programmable Gate Array (FPGA) and has been successfully synthesized and implemented with Xilinx Spartan-6 and Virtex-4 FPGA. Simulation results show that the proposed structure has high speed and excellent performance with low power consumption while having the lowest propagation delay (3.25 ns) and acceptable hardware utilization compared to existing squaring models. The gate-level design of 8-bit squaring is implemented using Cadence layout tools in 65 nm CMOS technology which has a total area of 0.095 mm2.