Hardware architecture design for complementary ensemble empirical mode decomposition algorithm

Abstract

In this paper, we have presented a field-programmable gate array (FPGA) as well as an application-specific integrated circuit (ASIC) based design for the complementary ensemble empirical mode decomposition (CEEMD) algorithm. CEEMD is an adaptive signal analysis method that decomposes an input signal into many signals, each of which is termed an intrinsic mode function (IMF). In this work, the CEEMD architecture is developed in the form of Verilog-HDL code. The ASIC is designed by using a 180 nm technology library. Our proposed ASIC can be operated at a clock rate of 58.82 MHz, and the total power dissipation of the ASIC is 76.20 mW. The core area of the CEEMD ASIC is 1.53 mm2. The FPGA-based design of CEEMD can work with a clock rate of 50 MHz, and Virtex-7 FPGA is used for the implementation purpose. The proposed parallel architecture of CEEMD extensively reduces the computational time of the design by employing parallel processing. FPGA and the ASIC-based design of CEEMD have very less computation time and can be used for real-time applications.