Abstract
The linear feedback shift register (LFSR) and Gold codes are used in telecommunications, Global Positioning System (GPS), satellite navigation, wireless systems, and code division multiple access (CDMA) dependent channel schemes for numerous radio communication technologies Gold codes are distinguished by their capacity to provide various orthogonal sequences.•The objective of the article is to focus on the design and simulation of the LFSR-based gold code generator chip in Xilinx ISE 14.7 software with the logic synthesis in Virtex-5 field programmable gate array (FPGA) and check the switching behavior with large frequency support applicable in fast-switching optical, and wireless electronics systems.•The methodology comprises design, functional simulation with different test inputs, and FPGA synthesis. The chip design is verified for the 10-bit seeding sequence of LFSRs to result in 1023-bit code with the frequency support of 310 MHz, and 9.285 ns delay.•The chip design is simulated based on seed data and different tap points of LFSR registers from which the bits are considered to generate the feedback. The design is scalable and has greater potential to extend to a larger extent. The behavior of the gold code depends on the maximum length sequence, absolute cross-correlation, and size of LFSR.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.