Virtex-5 Field Programmable Gate Array Research Articles

High-Speed and Adaptive FPGA-Based Privacy Amplification in Quantum Key Distribution

Privacy amplification (PA) is a vital procedure in quantum key distribution (QKD) to shrink the eavesdropper's information about the final key almost to zero. With the increase of repeat frequency of discrete variable QKD (DV-QKD) system, PA processing speed has become the bottleneck in many high-speed DV-QKD systems. In this paper, a high-speed adaptive field-programmable gate array (FPGA)-based PA scheme using a fast Fourier transform (FFT) is presented. To decrease the computation complexity, a modified 2-D FFT-based Toeplitz PA scheme is designed. To increase the processing speed of the scheme on the constraint of limited resources, a real-value oriented FFT acceleration method and a fast read/write balanced matrix transposition method are designed and implemented in our scheme. The experimental results on a Xilinx Virtex-6 FPGA demonstrate that the throughput is nearly double of the latest FPGA based Toeplitz PA scheme according to the literature. Besides, this scheme owns not only the good adaptivity to compression ratio but also the compression ratio independent resource consumption. Therefore, this scheme can fit many high-speed QKD applications.

Efficient Hardware Implementation of Modular Arithmetic and Group Operation Over Prime Field

The need for secure communication over the network has increased drastically over recent years, and Elliptic Curve Cryptography (ECC) carries out a significant role in moving secured information. In this work, a hardware implementation of modular arithmetic and group operations over the prime field for an Elliptic Curve Cryptography Processor (ECP) for an efficient security system is proposed. The modular addition or subtraction operation takes only one clock cycle and the modular multiplication, which is designed using the interleaved modular multiplication method, requires 257 clock cycles. For elliptic curve group operation separate point doubling (PD) and point addition (PA) architectures are implemented in Jacobean coordinates. These new architectures are simulated in a Xilinx ISE 14.7. After that, the architectures are implemented in Xilinx Virtex-7 field-programmable gate array (FPGA) with the VHDL language. Proposed modular arithmetic and group operations can be utilized to design an Elliptic Curve Point Multiplication (ECPM).

A real-time, high-accuracy, hardware-based integrated parameter estimator for deep space navigation and planetary radio science experiments

Real-time, high-accuracy frequency-phase estimation is the critical mission of Doppler tracking, which is a primary technique for deep space spacecraft navigation and planetary radio science experiments. Usually, the analog intermediate frequency signal is digitalized and converted to baseband by signal processing hardware platforms called digital back-ends (DBEs) and parameter estimation is performed by extra high performance computers. In this paper, a novel real-time, high-accuracy parameter estimator called a hardware-based integrated parameter estimator (HIPE) is proposed and implemented inside DBEs. An adaptive frequency tracker is proposed to make the initial signal detection, frequency tracking, and data reduction. Then a parameter estimation is sequentially obtained by a modified dechirp technique and a high-resolution spectral analysis technique called spec-zooming. Further, a folding architecture is designed to save hardware resources when realizing spec-zooming in a field programmable gate array (FPGA). An example design is deployed on a DBE with Xilinx Virtex-6 FPGA and an ARM processor. The performance is verified by X-band observations of Mars Express (MEX) and New Horizons (NH). Under an integration time of 1 s, HIPE only takes 2.2 ms to process single-channel baseband data and provides frequency accuracies of 7 mHz and 30 mHz for the tested MEX and NH data. HIPE is implemented inside DBE, so the extra computer is no longer required and the pressure of data transmission or storage is greatly relieved. It could easily be extended to parallel multi-channel, real-time processing and would be a powerful method for Doppler measurement in deep space exploration missions, such as the Chinese mission to Mars to be undertaken by 2020.

Real-Time DSP-Enabled Digital Subcarrier Cross-Connect Based on Resampling Filters

A real-time digital signal processing (DSP)- enabled digital subcarrier cross-connect (DSXC) with resampling filters for channel frequency translation is demonstrated in this paper. This circuit-based DSXC supports flexible and fine data-rate subcarrier channel granularities, offering a low-latency data plane, transparency to modulation formats, and the capability of compensating for transmission impairments in the digital domain. The presented 8 × 8 DSXC demonstrator makes use of a Virtex-7 field programmable gate array (FPGA) platform, which supports any-to-any switching of eight subcarrier channels with mixed modulation formats and data rates. Digital resampling filters enable frequency translation of subcarrier channels at the cross-connect with much reduced processing requirements for the FPGA resources in comparison to the traditional technique based on in-phase/quadrature mixing and filtering.

A Reconfigurable Hardware Architecture for Principal Component Analysis

Principal component analysis (PCA) is one of the widely used techniques for dimensionality reduction in multivariate statistical analysis. This article presents an efficient architecture design and implementation of the PCA algorithm on a field-programmable gate array (FPGA). The designed reconfigurable architecture is modeled in both floating-point and fixed-point representations using our custom-developed library of numerical operations. The PCA architecture supports input dataset matrices with parameterizable dimensions. The synthesizable model of the PCA architecture is modeled in Verilog hardware description language, and its cycle-accurate and bit-true simulation results are verified against its software simulation models. The characteristics and implementation results of the PCA architecture on a Xilinx Virtex-7 FPGA and in a standard 45-nm CMOS technology are presented. The execution times of the implemented PCA system on the FPGA for different data sizes are compared with those of the graphics processing unit and general-purpose processor implementations. To the best of our knowledge, this work is the first high-throughput design and implementation of the reconfigurable PCA architecture, including both the learning and mapping phases, on a single FPGA.

A Low-Complexity Hardware for Deterministic Compressive Sensing Reconstruction

Reconstruction algorithms of compressively sampled data include solving a sparse approximation problem. This problem requires iterative search or optimization techniques. Software implementations are not fast enough for real-time applications of recovery algorithms and these algorithms should be implemented in hardware. This paper presents a low-complexity hardware for real-time reconstruction of compressively sensed signal using orthogonal matching pursuit algorithm. The main goal of this research is to provide a deterministic alternative to the random measurement matrix. The construction of this matrix is based on the connection between the parity check matrix of low-density parity-check (LDPC) codes and the measurement matrix of compressive sensing. For efficient hardware realization, a geometric approach to the construction of LDPC codes is used for matrix generation on the fly without requiring a lot of storage. Cyclic and binary structure of this matrix leads to the lower computational complexity and hardware cost in the reconstruction side. The described hardware has been implemented and evaluated on a virtex6 field-programmable gate array from Xilinx. Implementation results show that the proposed architecture has better performance in terms of hardware utilization. Moreover, the accuracy of the recovered signal is comparable with the previous works in which the random measurement matrix is used.

EE-TCAM: An Energy-Efficient SRAM-Based TCAM on FPGA

Ternary content-addressable memories (TCAMs) are used to design high-speed search engines. TCAM is implemented on application-specific integrated circuit (native TCAMs) and field-programmable gate array (FPGA) (static random-access memory (SRAM)-based TCAMs) platforms but both have the drawback of high power consumption. This paper presents a pre-classifier-based architecture for an energy-efficient SRAM-based TCAM. The first classification stage divides the TCAM table into several sub-tables of balanced size. The second SRAM-based implementation stage maps each of the resultant TCAM sub-tables to a separate row of configured SRAM blocks in the architecture. The proposed architecture selectively activates at most one row of SRAM blocks for each incoming TCAM word. Compared with the existing SRAM-based TCAM designs on FPGAs, the proposed design consumes significantly reduced energy as it activates a part of SRAM memory used for lookup rather than the entire SRAM memory as in the previous schemes. We implemented the proposed approach sample designs of size 512 × 36 on Xilinx Virtex-6 FPGA. The experimental results showed that the proposed design achieved at least three times lower power consumption per performance than other SRAM-based TCAM architectures.

Fast Content Updating Algorithm for an SRAM-Based TCAM on FPGA

Static random-access memory (SRAM)-based ternary content-addressable memory (TCAM), an alternative to traditional TCAM, where inclusion of SRAM improves the memory access speed, scalability, cost, and storage density compared to conventional TCAM. In order to confidently use the SRAM-based TCAMs in application, an update module (UM) is essential. The UM replaces the old TCAM contents with fresh contents. This letter proposes a fast update mechanism for an SRAM-based TCAM and implements it on Xilinx Virtex-6 field-programmable gate array. To the best of authors’ knowledge, this is the first ever proposal on content-update-module in an SRAM-based TCAM, which consumes least possible clock cycles to update a TCAM word.

An Efficient Hardware Implementation for a Motor Imagery Brain Computer Interface System

Brain Computer Interface (BCI) systems, which are based on motor imagery, enable human to command artificial peripherals by merely thinking to the task. There is a tremendous interest in implementing BCIs on portable platforms, such as Field Programmable Gate Arrays (FPGAs) due to their low-cost, low-power and portability characteristics. This article presents the design and implementation of a Brain Computer Interface (BCI) system based on motor imagery on a Virtex-6 FPGA. In order to design an accurate algorithm, the proposed method avails statistical learning methods such as Mutual Information (MI), Linear Discriminant Analysis (LDA) and Support Vector Machine (SVM). It also uses Separable Common Spatio Spectral Pattern (SCSSP) method in order to extract features. Simulation results prove achieved performances of 73.54% for BCI Competition III-dataset V, 67.2% for BCI Competition IV-dataset 2a with all four classes, 80.55% for BCI Competition IV-dataset 2a with the first two classes, and 81.9% for captured signals. Moreover, the final reported hardware resources determine its efficiency as a result of using retiming and folding techniques from the VLSI architecture perspective. The complete proposed BCI system not only achieves excellent recognition accuracy but also remarkable implementation efficiency in terms of portability, power, time, and cost.

High‐throughput and compact reconfigurable architectures for recursive filters

This study presents various high-throughput reconfigurable architectures and their hardware implementation characteristics for infinite impulse response (IIR) filters. It is known that finite word length effects can be alleviated, to some extent, by realising a high-order IIR filter using the cascade of lower-order filter sections. The authors utilise the cascade structure of the first-order and second-order filters and apply a set of optimisation techniques, such as cutset retiming, look-ahead transformations, and interleaving for high-throughput realisations of IIR filters. Since the cascade structure may require a relatively large number of computational resources and storage elements, which depends linearly on the number of sections, the authors also present a filter processor architecture for the compact implementation of IIR filters. Filter architectures are developed in the fully parameterisable fixed-point representation and verified against their synthesisable Verilog descriptions. The authors present the implementation results of the transformed filter architectures on a Xilinx Virtex-7 field-programmable gate array (FPGA). To the best of their knowledge, this is the first presentation of various high-throughput and compact IIR filter architectures and their FPGA implementation characteristics.

Reconfigurable Hardware Architecture for Authenticated Key Agreement Protocol Over Binary Edwards Curve

In this article, we present a high-performance hardware architecture for Elliptic curve based (authenticated) key agreement protocol “Elliptic Curve Menezes, Qu and Vanstone” (ECMQV) over Binary Edwards Curve (BEC). We begin by analyzing inversion module on a 251-bit binary field. Subsequently, we present Field Programmable Gate Array (FPGA) implementations of the unified formula for computing elliptic curve point addition on BEC in affine and projective coordinates and investigate the relative performance of these two coordinates. Then, we implement the w -coordinate based differential addition formulae suitable for usage in Montgomery ladder. Next, we present a novel hardware architecture of BEC point multiplication using mixed w -coordinates of the Montgomery laddering algorithm and analyze it in terms of resistance to Simple Power Analysis (SPA) attack. In order to improve the performance, the architecture utilizes registers efficiently and uses efficient scheduling mechanisms for the BEC arithmetic implementations. Our implementation results show that the proposed architecture is resistant against SPA attack and yields a better performance when compared to the existing state-of-the-art BEC designs for computing point multiplication (PM). Finally, we present an FPGA design of ECMQV key agreement protocol using BEC defined over GF(2 251 ). The execution of ECMQV protocol takes 66.47μs using 32,479 slices on Virtex-4 FPGA and 52.34μs using 15,988 slices on Virtex-5 FPGA. To the best of our knowledge, this is the first FPGA design of the ECMQV protocol using BEC.

Synthesis of an Application Specific Instruction Set Processor (ASIP) for RIPEMD-160 Hash Algorithm

ABSTRACTHash functions are vital tasks in many applications such as digital fingerprinting, Internet communications, bank transactions and so forth. RACE Integrity Primitives Evaluation Message Digest-160 (RIPEMD-160) is one of the most applicable hash functions that there have been several structures for designing it based on Application-Specific Integrated Circuit (ASIC) approach in the literature. Application-Specific Instruction Set Processor (ASIP) design makes compromise between ASIC and Digital Signal Processing approaches with respect to speed, cost and flexibility. Because of this unique property of ASIP method, an ASIP processor for RIPEMD-160 hash algorithm is presented in this article for the first time. A special Register Configuration (RC) for RIPEMD-160 hash algorithm is developed which its Instruction Set Architecture (ISA) includes 12 specific and 35 general instructions. Proposed ASIP is simulated with VHDL language in the behavioural level of abstraction, and a typical assembly code is written to show how the proposed ASIP performs hash function. Moreover, implementation results on Virtex5 Field Programmable Gate Array (FPGA) platform shows the superiority of the proposed processor in terms of performance against its counterparts.

Hardware Implementation and Performance Analysis of Resource Efficient Probabilistic Hard Decision LDPC Decoders

The Gallager B (GaB), among the hard-decision class of low-density-parity-check (LDPC) algorithms, is an ideal candidate for designing high-throughput decoder hardware. However, GaB suffers from poor error-correction performance. We introduce a probabilistic GaB (PGaB) algorithm that disturbs the decisions made during the decoding iterations randomly with a probability value determined based on experimental studies. We propose a heuristic that switches the decoding from GaB to PGaB after certain number of iterations and show that our heuristic reduces the average iteration count by up to 62% compared with GaB. We evaluate the hardware performance and resource requirement trends of PGaB over three quasicyclic codes using the Xilinx Virtex-6 field programmable gate array. We extend this analysis to performance comparison over our implementations of gradient descent bit flipping (GDBF) and probabilistic GDBF (PGDBF) algorithms for each code studied in this paper. We achieve up to four orders of magnitude better error correction performance than the GaB with less than 1% loss in throughput performance. Our heuristic consistently results with an improvement in maximum operational clock rate across all codes compared with the GDBF and PGDBF.

Automated Scalable Address Generation Patterns for 2-Dimensional Folding Schemes in Radix-2 FFT Implementations

Hardware-based implementations of the Fast Fourier Transform (FFT) are highly regarded as they provide improved performance characteristics with respect to software-based sequential solutions. Due to the high number of operations involved in calculations, most hardware-based FFT approaches completely or partially fold their structure to achieve an efficient use of resources. A folding operation requires a permutation block, which is typically implemented using either permutation logic or address generation. Addressing schemes offer resource-efficient advantages when compared to permutation logic. We propose a systematic and scalable procedure for generating permutation-based address patterns for any power-of-2 transform size algorithm and any folding factor in FFT cores. To support this procedure, we develop a mathematical formulation based on Kronecker products algebra for address sequence generation and data flow pattern in FFT core computations, a well-defined procedure for scaling address generation schemes, and an improved approach in the overall automated generation of FFT cores. We have also performed an analysis and comparison of the proposed hardware design performance with respect to a similar strategy reported in the recent literature in terms of clock latency, performance, and hardware resources. Evaluations were carried on a Xilinx Virtex-7 FPGA (Field Programmable Gate Array) used as implementation target.

Decimal multiplication using compressor based-BCD to binary converter

The objective of this work is to implement a scalable decimal to binary converter from 8 to 64 bits (i.e 2-digit to 16-digit) using parallel architecture. The proposed converters, along with binary coded decimal (BCD) adder and binary to BCD converters, are used in parallel implementation of Urdhva Triyakbhyam (UT)-based 32-bit BCD multiplier. To increase the performance, compressor circuits were used in converters and multiplier. The designed hardware circuits were verified by behavioural and post layout simulations. The implementation was carried out using Virtex-6 Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) with 90-nm technology library platforms. The results on FPGA shows that compressor based converters and multipliers produced less amount of propagation delay with a slight increase of hardware resources. In case of ASIC implementation, a compressor based converter delay is equivalent to conventional converter with a slight increase of gate count. However, the reduction of delay is evident in case of compressor based multiplier.

The Implementation of the Improved OMP for AIC Reconstruction Based on Parallel Index Selection

Sparse signal recovery becomes extremely challenging for a variety of real-time applications. In this paper, we improve the orthogonal matching pursuit (OMP) algorithm based on parallel correlation indices selection mechanism in each iteration and Goldschmidt algorithm. Simulation results show that the improved OMP algorithm with a reduced number of iterations and low hardware complexity of matrix operations has higher success rate and recovery signal-to-noise-ratio (RSNR) for sparse signal recovery. This paper presents an efficient complexvalued system hardware architecture of the recovery algorithm for analog-to-information structure based on compressive sensing. The proposed architecture is implemented and validated on the Xilinx Virtex6 field-programmable gate array (FPGA) for signal reconstruction with N = 1024, K = 36, and M = 256. The implementation results showed that the improved OMP algorithm achieved a higher RSNR of 31.04 dB compared with the original OMP algorithm. This synthesized design consumes a few percentages of the hardware resources of the FPGA chip with the clock frequency of 135.4 MHZ and reconstruction time of 170 μs, which is faster than the existing design.

MIMO Detector for LTE/LTE-A Uplink Receiver

We propose a carefully selected receiver structure, detector and detector implementation architecture for multiple-input multiple-output (MIMO) uplink base station receiver for fourth generation (4G) wireless cellular systems. First, we compare different receiver algorithms and structures for single-carrier frequency-division multiple access (SC-FDMA) uplink transmission to get a good understanding of the performance and complexity of these algorithms and their suitability for practical realization. One of those structures, namely the frequency domain MMSE equalization with sphere detection (SD), is proposed for implementation. The receiver consists of separate stages for inter-symbol interference (ISI) and inter-antenna interference (IAI) mitigation in frequency selective MIMO channels. Frame error rate (FER) performance is studied via simulations in realistic wireless channels and practical system parameters. K-best SD is selected as a detector algorithm for this receiver. There are several publications proposing a sort-free architecture for tree search type of detectors. Both a conventional K-best architecture and a sort-free architecture are implemented on a Xilinx Virtex-6 field-programmable gate array (FPGA) using High Level Synthesis (HLS) tool. Both architectures support 4 × 4 MIMO with 64-level modulation (64-QAM). Complexity results confirm that avoiding the sorter is not always recommended. The benefit of sort-free architecture depends on the system parameters.

Hardware implementation of multi-objective differential evolution algorithm: a case study of spectrum allocation in cognitive radio networks

In this paper, a hardware solution for multi-objective differential evolution (MODE) algorithm is presented. The proposed hardware is developed as a co-processor and interfaced with PowerPC440 processor of Virtex-5 field programmable gate array to accelerate execution speed on an embedded platform. It is validated by optimising four standard benchmark functions and its execution time is compared with the same algorithm running on a 32-bit PowerPC440 processor. Further, as a case study, the proposed hardware is used to solve Spectrum Allocation (SA) problem in Cognitive Radio Network (CRN). In CRN, the available licensed channels are assigned to cognitive users using SA task while satisfying the multiple objectives posed by licensed users. The MODE core is integrated with the SA objective functions and developed as a MODE-based SA (MODE-SA) co-processor on an embedded platform for distributed CRN. The MODE-SA core has attained a speedup of 50-60× compared to the PowerPC440 implementation.

2D Parallel Architecture for Morphological Operators Supporting Multiple Shaped Structuring Elements

This paper presents a reconfigurable 2D parallel architecture designed to implement efficiently two fundamental gray scale morphological operations: dilation and erosion. The architecture is expected to be used as a hardware core integrated in real time application. Moreover, the proposed architecture allows processing data on high resolution images with reconfigurable size and arbitrary shape of structuring elements. The main advantage of the proposed architecture is its low latency, higher throughput and higher processing frame rate. Additionally, the architecture processes data on stream which avoids the need of any buffering at input level. The architecture is successfully implemented and prototyped on Virtex-5 field programmable gate array. Implementation results show that the architecture can achieve high frame rate: for example, for a 1024x768 image and 11x11 structuring element, we reach a frame rate of 341 Fps.

Design of MIMO K-Best Detection Algorithm And Its FPGA Implementation

Based on the research of MIMO Detection Algorithms theory and implementation methods, here novel k-Best MIMO detection algorithm is presented. Proposed algorithm uses an estimate technique and parallel sort approaches, which reduces the computational difficulty, and adopts pipelined configuration in parallel to save computation time. This algorithm implemented on Xilinx virtex-6. Implementation of proposed k-best multiple input multiple output detection algorithm on Field Programmable Gate Array is a challenging task by considering area and power. Computational complexity and resource utilization of this algorithm is discussed by implementing it on Virtex Field Programmable Gate Array. Field Programmable Gate Array implementation attained a good trade-off between power and area compared to the previous designs. Because of pipelined design and sorting procedure it is well suited for FPGA implementation and achieved 2.8 Gbps throughput for 64QAM modulation scheme with 4x4 systems. The flexibility of the scheme permits the high performance detection with low power consumption.