Design of MIMO K-Best Detection Algorithm And Its FPGA Implementation

Abstract

Based on the research of MIMO Detection Algorithms theory and implementation methods, here novel k-Best MIMO detection algorithm is presented. Proposed algorithm uses an estimate technique and parallel sort approaches, which reduces the computational difficulty, and adopts pipelined configuration in parallel to save computation time. This algorithm implemented on Xilinx virtex-6. Implementation of proposed k-best multiple input multiple output detection algorithm on Field Programmable Gate Array is a challenging task by considering area and power. Computational complexity and resource utilization of this algorithm is discussed by implementing it on Virtex Field Programmable Gate Array. Field Programmable Gate Array implementation attained a good trade-off between power and area compared to the previous designs. Because of pipelined design and sorting procedure it is well suited for FPGA implementation and achieved 2.8 Gbps throughput for 64QAM modulation scheme with 4x4 systems. The flexibility of the scheme permits the high performance detection with low power consumption.