Built-In Self-Test of programmable clock buffers in Virtex-4, Virtex-5 and Virtex-6 FPGAs

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We present a modified Built-In Self-Test (BIST) approach for programmable clock buffers in Xilinx Virtex-4, Virtex-5, and Virtex-6 Field Programmable Gate Arrays (FPGAs). While seemingly trivial, these critical clock buffer modules present interesting testing challenges as will be described in this paper. A timing problem was found in the previously reported BIST approach for the clock buffers [1], where the simultaneous switching of inputs to the clock buffers can produce different responses which result in a BIST failure indications in a fault-free device. In addition, the previous approach used normal signal routing resources to route the clock signal to BIST circuitry instead of dedicated clock routing resources, and this may have contributed to the timing problem. We present and discuss modifications that solve the timing problem as well as their impact on the maximum BIST clock frequency and total test time based on implementation and execution in actual Virtex-4 and Virtex-5 FPGAs. <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup>