VHDL Model Research Articles

Medium Access Control CSMA/CA Binary Countdown Protocol for SCADA Application

This paper discusses a novel approach toaccess the medium using CSMA/CA (Carrier Sense Multiple Access with Collision Avoidance) protocols for SCADA ( S upervisory C ontrol A nd D ata A cquisition) system employed in power systemoperation and control. This method offers superior performance over the existing practices of accessing medium using CSMA/CD protocols. The proposal makes use of binary countdown method with modifications. The requirements of SCADA system such as reliability and real time operation can be achieved by fast data transmission and prompt delivery. In this work, a program is written and the procedure is run to allocate the channel considering the priorities of the RTUs (Remote Terminal Units) and the type of data to be transmitted such as normal data for archival and event triggered data for operation control. The program uses generic statement and is applicable to a system having a MTU (Master Terminal Unit) and any number of RTUs. The results obtained by running the procedure show its novelty. Further, a Moore finite state Moore machine is designed and a VHDL model is developed

A massively parallel pipelined reconfigurable design for M-PLN based neural networks for efficient image classification

Weightless Neural Networks (WNNs) are a powerful mechanism for pattern recognition. Aiming at enhancing their learning capabilities, Multi-valued Probabilistic Logic Nodes (M-PLN) are used, instead of crisp neurons with a 0/1 based RAM-nodes. An M-PLN stores a mapping of, or possibly, the triggering probability, for each input pattern that needs to be recognized. The M-PLN model attempts to strengthen the discrepancies between distinct patterns used during the training process and those that have not yet been processed. In this paper, an efficient yet customizable hardware architecture for M-PLN based neural network is proposed. It implements the learning and operation processes of a pyramidal network structure, augmented by a probabilistic rewarding/punishing search algorithm. The training algorithm can adapt itself to the overall hit ratio so far achieved by the network. Using class-dedicated layers, the hardware is able to handle image classification in parallel and thus, very efficiently. Furthermore, the classification process is performed in a pipelined manner so its stages never stop working until all input images are classified. Nonetheless, during network training, only one of these layers is activated. Last but not least, the architecture is customizable as its structure can be tailored in accordance to the application characteristics in terms of class number, pattern tuple size and image resolution. In order to evaluate the time and cost requirements of the proposed design, its underlying architecture was specified in VHDL and functionally tested. The presented results are two-fold: first, based on many functional simulations, estimated time and cost requirements are analyzed; second, to further assess the performance of the proposed the design, the VHDL model was synthesized to produce a semi-custom implementation on FPGAs. We also give an assessment of the quality of the entailed classification process. The architecture exhibits performance and reconfiguration capabilities that are very promising and encouraging towards the fabrication of a prototype on ASIC.

An Efficient Functional Test Generation Method For Processors Using Genetic Algorithms

Abstract The paper presents a new functional test generation method for processors testing based on genetic algorithms and evolutionary strategies. The tests are generated over an instruction set architecture and a processor description. Such functional tests belong to the software-oriented testing. Quality of the tests is evaluated by code coverage of the processor description using simulation. The presented test generation method uses VHDL models of processors and the professional simulator ModelSim. The rules, parameters and fitness functions were defined for various genetic algorithms used in automatic test generation. Functionality and effectiveness were evaluated using the RISC type processor DP32.

A Hardware Implementation of Arithmetic Operations for an FPGA-based Programmable Logic Controller

The paper presents the Arithmetic and Logic Unit (ALU) of a prototype Programmable Logic Controller (PLC), implemented in an FPGA device. The PLC implements on the machine language level a subset of the instruction set defined in the EN 61131-3 norm. The design was prepared as a set of synthesizable Verilog, and VHDL models. The ALU can execute 32 operations, which include the basic logic operations, comparators, and the four basic arithmetic operations. The operations can be performed for fixed-point, and floating-point numbers. All the operations are implemented fully in hardware, so the solution is fast. The HDL models used for synthesis can be easily ported to other FPGA architectures, or to an ASIC.

English

In this work, we show a VHDL-based technique to guesstimate precise power dissipation of a mean considering the state-craving of the leakage power and conduit dependency of dynamic power. We build up the VHDL models of cells which mark out the prospect of the static levels of the signals in the track of a simulation. Then, these facts are utilized to compute the power dissipation in the taken as a whole design. The power dissipation of a quantity of standard circuits is estimated via the planned approach. Profound submicron technology on creates a new set of design setbacks. Leading to a power mass and whole power dissipation that is at the bounds of what packaging, chilling, and other communications can support. The leakage current is rising radically, to the position where, in some 65nm designs, leakage current is virtually as huge as dynamic current.

Subword Partition based Data Driven Clock Gating Scheme for Low Power VLSI Design

low power optimization has been major concern in VLSI design from last two decades. The work presented here analyzes various clock gating based power optimization techniques in the context of digital signal processing applications. The clock gating based techniques with architecture level optimization possibilities are discussed. A novel method for data specific clock gating based on subword partition is developed and same is verified on Transposed FIR filter structure. The generic VHDL models of subword datapath based FIR architectures are used along with Xilinx Vivado power and performance analysis tools for validation. The results show power optimization upto 47% for narrowband input signal conditions on Virtex-6 Lx240T FPGA. The research shows a promising direction of power optimization technique, which can be used for wide range of signal processing applications.

IMPLEMENTATION OF GPS SIGNAL ACQUISITION AND TRACKING IN FPGA

GPS Receivers are used for both military and civilian applications. This paper presents the GPS Receiver for System on Chip (SoC) application. In this paper the GPS Receiver is been implemented as System on Chip in FPGA board. VHDL modeling for the back end of GPS Receiver is designed. As baseband signal processing is the main aspect in the GPS receiver, it is achieved by this software GPS Receiver. Here the acquisition and tracking of the GPS signals is been designed and the data is recovered. MODEL SIM simulator is used here to validate the VHDL modeling. Hence the software defined GPS Receiver is simulated and implemented in FPGA for navigation purpose along with an analog front end.

A 0.07 mm$^2$ Asynchronous Logic CMOS Pulsed Receiver Based on Radio Events Self-Synchronization

This paper presents an ultra-low-power radio receiver implemented only with CMOS logic gates used as basic building blocks and proves its operation. The self-timed duty-cycled system is self-synchronized with the input radio signal, runs a noise-robust baseband detection and does not require any reference besides power supply. Based on S-OOK modulation, the 350-450 MHz digital radio RX occupies an area of 0.07 mm 2 in a 130 nm RFCMOS technology and achieves a 0.1% sensitivity of -63 dBm at 95 kbps, 380 MHz center frequency and 40 μW active power consumption at 1.1 V power supply. At 1.0 V it achieves -62 dBm sensitivity and 33 μW active power at ~ 0.1% error rate. The compact receiver, whose architecture is parametric and technology scalable, suits energy harvested and miniaturized biomedical applications. The paper also presents the potential advantages of asynchronous logic pulse radio and introduces an ad-hoc VHDL model demonstrating RTL-/gate-level accurate error-rate predictions capabilities based on digital simulation only, i.e., without requiring electrical-level co-simulation.

Memory Efficient LUT Based Address Generator for OFDM-WiMAX De-Interleaver

In this paper, a memory efficient Look-up Table (LUT) based address generator for the de-interleaver used in OFDM-WiMAXtransreceiver is proposed. The relationships between various address LUTs implementing different interleaver / de-interleaver depths within a modulation scheme have been exploited to model the proposed address generator. The proposed design shows 81.25% saving of memory blocks in comparison with conventional technique. Hardware structure of the address generator is developed and is converted into a VHDL model using Xilinx Integrated Software Environment (ISE). Simulation results obtained using ModelSim XE-III verifies the functionality of the proposed design. Comparative study of FPGA implementation results of the design on two different platforms is presented. Performance improvement of approximately 30% in terms of maximum operating frequency over a recent work is also obtained. 

Design Automation of Neural Network Applications Using Formal Techniques—Rapid Prototyping Using the CCC Synthesizer

Cellular neural network (CNN) implementations used in real time image processing are rapidly generated by a formal High-level synthesis (HLS) toolset in this work. Industrial and academic hardware design projects can benefit from the use of the Custom Coprocessors Compilation (CCC) HLS behavioral synthesise, via the massive reduction in design and verification time. The CCC tool is built with formal compiler-compiler, Logic Programming and XML validation techniques, thus the generated RTL VHDL or Verilog models are provably-correct. In this work, we rapidly modeled CNNs in the ADA programming language, compiled and verified along with all the necessary testbenches in GNU ADA. Edge-detection, halftoning and morphological processing applications were prototyped, so as to evaluate the CCC HLS method, which was the main contribution of this work. The combination of Logic Programming and RDF validation techniques, as well as prototyping of CNN applications made this work unique.

Reconfigurable Digital multiple beam forming with planar phased array RADAR on FPGA

Beam forming is a signal processing technique used in antenna arrays for directional signal transmission or reception. Phased array radar is very important in modern radar development, and multiple digital beams forming technology is the most significant technology in phased array radar. Digital multiple beam forming on each antenna element about large phased array radar is impossible in processor based digital processing units, because it needs simultaneous processing many A/D channels.In this project we resolve this problem by using a multi array based beam forming technique with multiplexed signal processing unit on FPGA. The conventional technique of completely duplicated hardware and also dynamic reconfiguration does not yield the real time parallel beam processing. The proposed technique employs multiplexed signal processing unit which is time shared for various beam formers. This technique provides simultaneous beams without any compromise on functionality. The scope of the work includes the VHDL modeling of 16 element phased array antenna system and RTL implementation of complex NCO, digital mixer, low pass filter, multiplexers, demultiplexers, ROM for coefficient storage and Multiplier unit. The VHDL simulation of all these blocks shall demonstrate the beam formation for multiple beams. Simulated antenna outputs are used to test the developed beam former. The design is functionally verified by simulating the code in ModelSim from Mentor Graphics. The FPGA synthesis is done using Xilinx ISE tool. The synthesis results of ISE are analyzed for timing and area. The hardware output i.e FPGA output shows on Chipscope pro analyzer.

High efficiency MAC unit used in digital signal processing and elliptic curve cryptography

Computational complexities of different Algorithms to enhance the speed of response of digital signal processor and different cryptographic analysis are the important issues for the current researcher. Computational complexities means hardware complexities and timing complexities. Both the complexities depend on the design of the software and hardware. Arithmetic computation like addition and multiplication are the major parts in designing processor that helps to improve the efficiency and to reduce complexities. Hence the design of a multiplier unit is the major issue to the current researchers. There are different multiplication algorithms discussed in different research materials. In this paper, a new algorithm for multiplication has been proposed to enhance the speed of operation and to reduce hardware complexities. Also a comparative study of the proposed algorithm over different existing algorithms has been explained here along with VHDL model of the proposed architecture.

A VHDL Model for Implementation of MD5 Hash Algorithm

A VHDL Model for Implementation of MD5 Hash Algorithm

The use of models of incompletely specified Boolean functions in logical circuit synthesis based on VHDL descriptions

VHDL models for incompletely specified Boolean functions and systems of functions are proposed. It is shown that the use of such models makes it possible to obtain simpler logical circuits as opposed to implementing standard VHDL structures in some cases.

APPLICATION SPECIFIC INTEGRATED CIRCUITS DESIGN AND IMPLEMENTATION OF RADEMACHER AND WALSH FUNCTIONS

The orthogonal functions, specially the Rademacher and Walsh functions are being increasingly used in Digital Signal Processing (DSP). Today’s DSP applications require fast processing time in order to meet the challenges of the real time systems. State-of-the-art implementation technologies are therefore being used. This study describes the design and implementation of Rademacher and Walsh functions targeted to the state-of-the-art Cell Based Integrated Circuits (CBIC) technology. High level design techniques are used with the help of advanced EDA tools from SYNOPSYS International. Optimized VHDL models have been developed and used for design entry. The design is thoroughly verified using advanced verifications tools. The design is implemented and processing has been done with 90 nm CMOS Technology from TSMC foundry. It is observed that the results obtained, are far better than the FPGA implementation reported earlier in the literature.

SEU Fault-Injection in VHDL-Based Processors: A Case Study

Evaluating the sensibility of a given circuit with respect to soft errors became a main issue especially if it is intended to operate in space or at high altitudes. A hardware/software (HW/SW) approach to study the effects of soft errors by fault injection in the VHDL model of a CPU (Control Processor Unit) is presented and illustrated by results obtained for a LEON3 processor. The LEON3 is set to execute two benchmark algorithms. The first one is a typical 3x3 matrix multiplication, whereas the second one is a self-converging algorithm which is intended to provide correct results even if a failure occurs in the middle of the execution. The results of fault-injection campaigns targeting the register file unit of the processor are compared to those issued from a state-of-the-art method, the C.E.U. (Code Emulated Upset). One of the main advantages of the proposed method is the larger targeted Single Event Upset (SEU) sensitive area leading to improved error rate predictions.

A novel VLSI architecture for a fuzzy inference processor using Gaussian-shaped membership function

The widespread application of fuzzy logic in various fields has been hindered by the problem of low speed of operation of fuzzy processors. Both hardware and software approaches have been adopted to increase the speed of operation of the fuzzy processors in general and inference processing in particular. To improve the inference processing, the calculation of matching degree MD between the fuzzified input and the antecedent membership functions MF has to improve, as it needs very high latency and limits the overall inference performance. In this paper, a novel architecture of a MAX-MIN circuit, used for calculating the MD between two Gaussian-shaped MF's, used first time, has been proposed. The proposed architecture is area, power, speed efficient and flexible in comparison to existing architectures using trapezoid-MF, as the number of multiplexing and subtracting operations has been reduced. Further, based on the novel architecture of MAX-MIN calculator circuit, a novel fuzzifier, fuzzy decoder, fuzzy inferencing system and a complete fuzzy inference processor have been proposed and analyzed. The VHDL modeling and XILINX and Vertex based FPGA implementation of all proposed architectures have been performed.

Hardware / Software Co-design using LEON3 Processor: AES as Case Study

Nowadays many powerful public domain IP cores are available for complicated component like 32 bit processor i.e. LEON3. It needs considerable expertise and pain taking experimentation to implement a hardware/software co-design project. This paper presents step-by-step description for AES algorithm implementation on LEON3 processor. This will prove to be valuable to researchers working in this area and save their valuable time. The concept of GPIO (General Purpose I/O Port) is introduced; through which any custom hardware i.e. own designed hardware or IP core can be interfaced with the open source processor. AES encryption algorithm is selected as an IP core to be interfaced with LEON3 processor. AES is implemented in VHDL, while the control of the algorithm is in software. AES algorithm partitioned in hardware and software. The complete algorithm in hardware and control of algorithm in software. The part of algorithm in hardware is interfaced with the system designed using processor as a custom hardware and performance parameters studied. AES implemented using Codesign approach. AES is the latest encryption standard used to protect confidential information like financial data for government and commercial use. The LEON3 is a synthesizable VHDL model of a 32-bit processor available under the GNU GPL license. The design is implemented on Cyclone II FPGA from Altera Corporation.

Studying the effects of intermittent faults on a microcontroller

As CMOS technology scales to the nanometer range, designers have to deal with a growing number and variety of fault types. Particularly, intermittent faults are expected to be an important issue in modern VLSI circuits. The complexity of manufacturing processes, producing residues and parameter variations, together with special aging mechanisms, may increase the presence of such faults. This work presents a case study of the impact of intermittent faults on the behavior of a commercial microcontroller. In order to carry out an exhaustive reliability assessment, the methodology used lies in VHDL-based fault injection technique. In this way, a set of intermittent fault models at logic and register transfer abstraction levels have been generated and injected in the VHDL model of the system. From the simulation traces, the occurrences of failures and latent errors have been logged. The impact of intermittent faults has been also compared to that got when injecting transient and permanent faults. Finally, some injection experiments have been reproduced in a RISC microprocessor and compared with those of the microcontroller.

Design and implementation of an improved arbitrary waveform generator based on Walsh functions

The design and implementation of a new method of generating arbitrary signals was attempted. This new system is based upon the use of Walsh functions, which are derived from Rademacher functions. The VHDL modeling and the Xilinx field programmable gate arrays (FPGA) implementation of the proposed circuit were made. Two Walsh circuits realized using counter and exclusive OR (XOR) gates mainly control the operation of the system. For area efficiency, suitable word lengths at every stage were designed accurately based on arithmetic rules and Matlab analysis. The implementation was targeted to 3 technologies from Xilinx - Spartan 3, Virtex E and Virtex 4. It was found that the proposed system is about two times faster than the previously reported designs. In addition, the occupied area in some cases is less than 25% of the earlier designs. Key words: Arbitrary waveform generation, Walsh functions, Rademacher functions, Walsh Circuit, VHDL Model.