Subword Partition based Data Driven Clock Gating Scheme for Low Power VLSI Design

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low power optimization has been major concern in VLSI design from last two decades. The work presented here analyzes various clock gating based power optimization techniques in the context of digital signal processing applications. The clock gating based techniques with architecture level optimization possibilities are discussed. A novel method for data specific clock gating based on subword partition is developed and same is verified on Transposed FIR filter structure. The generic VHDL models of subword datapath based FIR architectures are used along with Xilinx Vivado power and performance analysis tools for validation. The results show power optimization upto 47% for narrowband input signal conditions on Virtex-6 Lx240T FPGA. The research shows a promising direction of power optimization technique, which can be used for wide range of signal processing applications.