Physical Design, Power and Area Optimization of High Frequency Block at Smaller Technology Node

Abstract

The complexity involved in the physical design of an Integrated circuit (IC) has been increasing due to the continuous reduction in the area and increase in the frequency of the Integrated circuit. The leakage power consumption of the IC has been increasing due to the continuous technology scaling. The dynamic power consumption of the IC has been increasing due to the increase in the clock frequency. So, there is need for good physical design methodologies, power and area optimization techniques. In this paper, a novel physical design methodology has been proposed. In this methodology, different floor-planning of macros in the design are used to design block and the designs are named as Design1, Design2 and Design3. Power optimizations techniques like clock gating, power gating, multi-threshold voltage cells etc. are applied at each stage of physical design to reduce the power consumption. Area optimization techniques like multibit register banking, cell bounds etc. are used at each stage of physical design to reduce area. After analyzing the results of all the three designs with respect to area utilization, leakage power and Quality of results (QoR), it has been concluded the floorplan of Design1 is best compared to Design2 and Design3 because Design1 has 11.7% improvement in leakage power compared to that of Design3 and 3.81% improvement in the area utilization compared to that of Design3.