A Hardware Implementation of Arithmetic Operations for an FPGA-based Programmable Logic Controller

Abstract

The paper presents the Arithmetic and Logic Unit (ALU) of a prototype Programmable Logic Controller (PLC), implemented in an FPGA device. The PLC implements on the machine language level a subset of the instruction set defined in the EN 61131-3 norm. The design was prepared as a set of synthesizable Verilog, and VHDL models. The ALU can execute 32 operations, which include the basic logic operations, comparators, and the four basic arithmetic operations. The operations can be performed for fixed-point, and floating-point numbers. All the operations are implemented fully in hardware, so the solution is fast. The HDL models used for synthesis can be easily ported to other FPGA architectures, or to an ASIC.