Implementation of arithmatic logic unit using GDI technique

Abstract

Nowadays to handle the more challenges and complex task the demand of improving ability of a processor is increasing day by day which resulted in the more numbers of components fabricated on a single chip according to the Moore Law. But with increasing in component the noise increase's. The ALU is a one of the most basic operational unit in any processor. The ALU is heart of any system or any processor and the core component of the central processing unit CPU because mainly all the basic operations are performed by the help of ALU only. As the name ALU signifies arithmetic logic unit, hence it is used to perform the athematic and logical operation in a digital bits. So the ALU can be defined as the combinational unit which is used to perform its logical and arithmetic units. The purpose of this paper is to implement the Arithmetic Logic Unit (ALU) by a CMOS technique in 45nm. The tasks perform by ALU are Logic operation (OR, AND, EXOR) and Arithmetic operation (ADDER). All the logical operation are performed by the help of logic gates using GDI technology. The GDI is the most commonly used technique for power reduction as it reduces the number of gates used. This result is then given to the multiplexer and the result obtained is dependent on the input select line. This result obtained is calculated is in the term of average power and noise and compared with the different input value. The implementation take place in a software cadence virtuoso.