VLSI Research Articles

A Review on Low Power VLSI Design Models in Various Circuits

Low power design is one of the primary goals for any integrated circuits. Very Large-Scale Integration (VLSI) is a kind of Integrated Circuit (IC) that consists of hundreds and hundreds of transistor connection into a small chip. The communication and computer applications have grown very faster in the past decade due to the development of VLSI circuit design as microcontroller and microprocessors. However, still the research on VLSI are moving faster towards the scope of power and area minimization. The paper gives an overview about the recent methodologies that have been developed for the performance improvement of VLSI design and it shows the future directions of the areas that are to be concentrated on VLSI circuit design.

Chiral resolution of racemic amines in µ-reactor-crystallizer

• A semi-continuous microfluidic platform for the chiral separation process is developed. • The crystal is formed in µ-Crystallizer ∼ 33 times faster than the batch process. • The obtained diastereomeric salt from µ-Crystallizer is purer than the batch process. • A parametric map with concentration and flow rate is presented for the desired crystal. • The microfluidic process demonstrated here can be adopted for industrial application. The production of pure chiral drugs in a continuous manner is one of the major issues for pharmaceutical industries. A micro continuous process is developed for chiral separation of racemic molecules exploiting a “classical” method of diastereomer formation and subsequent crystallization. A flexible µ-reactor and µ-crystallizer are fabricated for the continuous production of diastereomer salt crystals from racemic α-phenylethylamine (I) where optically active L-(+)-tartaric acid (II) is used as a resolving agent. CD spectroscopy, UV–Vis spectroscopy, and other characterizations confirm that the diastereomeric salt obtained from the micro-continuous process is similar in quality if not better than that obtained from a conventional batch process. The process described here is capable to produce crystals at ∼ 33 times faster than the batch process at identical feed concentrations. The better control over crystals and faster resolution in this low-cost micro-continuous process offer industries a potential route for production through very-large-scale integration (VLSI).

Optimizing and Recuperating the Leakages in Low Voltage CMOS Circuits

With the advancement of technology, small and handy electronic devices are built with low supply voltage and lower power dissipation in designing deep submicron static CMOS circuits. Small devices scaling down with burst-mode type integrated circuits have two major challenges: area and power dissipation. This paper presents a method for decreasing dynamic power, area, and leakage of application-specific integrated circuits without sacrificing performance. The High Threshold Leakage Control Transistor, TG-Based Technique, Supply Voltage Scaling, Sleep Transistor approaches are covered, and a dynamic CMOS architecture with stack transistor. With certain area and delay considerations, these strategies are utilized to diminish both types of power dissipation in the CMOS logic designs.

Hybrid Design of Pseudo Random Number Generator Using Shift Register FPGA and CMOS VLSI

The proliferation of digital systems in various applications necessitates the development of efficient pseudo-random number generators (PRNGs) for cryptographic and data processing purposes. In this study, we present a novel approach to PRNG design, leveraging a hybrid combination of Shift Register Field-Programmable Gate Arrays (FPGA) and Complementary Metal-Oxide-Semiconductor (CMOS) Very Large-Scale Integration (VLSI) technology. This hybrid design capitalizes on the strengths of both FPGA and CMOS VLSI to achieve enhanced performance and versatility. The FPGA-based component of the PRNG system offers configurability and parallelism, allowing for rapid and customizable PRNG generation. The CMOS VLSI component, on the other hand, ensures low power consumption and compact integration, ideal for embedded applications. By combining these two technologies, the PRNG achieves a delicate balance between flexibility and efficiency. We evaluate the hybrid PRNG design through rigorous testing and analysis, including statistical tests, spectral tests, and computational performance assessments. Our results demonstrate that the hybrid PRNG outperforms standalone FPGA or CMOS-based PRNGs in terms of randomness, uniformity, and speed, making it suitable for a wide range of applications in cryptography, secure communications, and data processing. The hybrid PRNG design presented in this study not only contributes to the advancement of PRNG technology but also offers a versatile solution for engineers and researchers seeking to tailor their PRNG systems to specific application requirements while optimizing performance and energy efficiency.

A Timing-Based Split-Path Sensing Circuit for STT-MRAM.

Spin-transfer torque magnetoresistive random access memory (STT-MRAM) applications have received considerable attention as a possible alternative for universal memory applications because they offer a cost advantage comparable to that of a dynamic RAM with fast performance comparable to that of a static RAM, while solving the scaling issues faced by conventional MRAMs. However, owing to the decrease in supply voltage (VDD) and increase in process fluctuations, STT-MRAMs require an advanced sensing circuit (SC) to ensure a sufficient read yield in deep submicron technology. In this study, we propose a timing-based split-path SC (TSSC) that can achieve a greater read yield compared to a conventional split-path SC (SPSC) by employing a timing-based dynamic reference voltage technique to minimize the threshold voltage mismatch effects. Monte Carlo simulation results based on industry-compatible 28-nm model parameters reveal that the proposed TSSC method obtains a 42% higher read access pass yield at a nominal VDD of 1.0 V compared to the SPSC in terms of iso-area and -power, trading off 1.75× sensing time.

Novel Design of a Digital PLL for Power Reduction

Very large-scale integration (VLSI) circuits operating at ultra-low power are currently acquiring more attention from the research group and the industries too. Recently, the performance of many applications depends on the size and energy consumption of sensor nodes. The energy efficient sensor nodes with reduced size are much preferred among applications such as wireless sensor networks, pollution and plant monitoring. The biggest challenge faced by the VLSI designers in present day life is designing a product of new generation which operates on minimum possible power. Power consideration is the eventual design criteria in different real-life applications like pacemakers etc. Phase Locked Loop is a framework that produces an output which is in phase with the input signal. In Phase Locked Loop (PLL), the focus is at the input signal’s phase with its output oscillator signal’s phase and thus modifies the recurrence frequency of the Voltage Controlled Oscillator (VCO) for phase co-ordination. The output signal from the Phase Frequency Detector is utilized to control the oscillator in a feedback circle also. As an operational gadget, the PLL has wide scope of utilization in media transmission, PCs and electronic applications. In this paper, designing and analysis of PLL with numerous outputs has been proposed to be implemented by changing the closed loop frequency control framework PLL blocks. As such, highly effective, low power, ideal area chip can be used for PLL with four various yields as PLL 8x, PLL 4x, PLL 2x and PLL 1x with different frequencies separately. Likewise, it is planned to utilize multi-threshold or sleep transistors to minimize the leakage current in the circuit. Further, the execution or performance verification of various parameters of PLL are done to acquire negligible power. Direct toolbox YALMIP is used as programming solver as an optimization tool. In addition to this, another method of Non- dominated sorting genetic algorithm (NSGA-II) Correlation for optimization is also introduced between both the strategies to find the best outcomes.

Simulation and Analysis of Fully Adiabatic Circuit Designing with Single Power Clock for High-Frequency Low Power VLSI Circuits

Adiabatic logic guarantees vast diminishments of power utilization since it doesn't disperse power. This paper audits ongoing advancement in adiabatic circuits. First, the fully adiabatic circuit designing technology called as pass-transistor adiabatic logic (PTAL) is discussed. Next, the operation of the dual rail logic and the power clock supply with the logic operation of the PTAL technology is discussed. Further, many basic logic circuits using the PTAL technology are designed, compiled and simulated. Finally, the performance results, power dissipation, speed, efficiency and load analysis of the circuits are compared with the conventional and existing CMOS technology under same simulation conditions using standard 45nm technology with VDD = 1V and proves that even at high frequencies above 2GHz, it is able to outperform the dominating conventional CMOS logic designing in the field of power dissipation. The simulation results are provided to support our claim. We used 45nm technology for all our simulations.

Review on CNTFET: Recent Developments in Biosensors for Health Care Applications

Abstract: With the increasing use of high-performance component circuits (VLSI) in biosensing, there has been remarkable progress in the field of nanotechnology. The carbon nanotube is basically made of graphite sheets wrapped to form a tubeshaped structure, with a periodic boundary structure that makes a hexagon that never breaks. Carbon nanotube field-effect transistors (CNTFETs) have lower latency and power consumption compared to compatible CMOS devices, so they are considered a viable option to switch CMOS devices to VLSI circuits with very low power. Biomedical sensors have received a lot of attention in the field of health care. CNTFETs have a high potential to drive many technological advances in the industry due to their unique electrical structures of CNTs. In this review, we focus on the use of CNT-based FET (CNTFETs) in biomedical systems. It starts with the introduction of the device and discusses four applications where CNTFETs are used, namely covid-19, hearing aid, cholesterol, and cancer. Finally, we conclude the review with an overview of CNTFET in the medical field. Keywords: Biosensing, Nanomaterial, CNTFET, Covid-19, Hearing aid, Cholesterol, and Cancer

Intelligent and kernelized placement: A survey

Placement is a crucial and time-consuming step in modern very-large scale integration (VLSI) physical design. In this survey, we provide a comprehensive review of existing machine learning techniques for placement studies and categorize them as follows: intelligent placement and kernelized placement. Intelligent placement that combines machine-learning algorithms and traditional placement methods will continue to be a trending topic in academic research. Kernelized placement frameworks that can significantly accelerate solving multi-objective placement problems using AI hardware have also received considerable attention recently. We discuss the advantages and drawbacks of intelligent placement and kernelized placement and highlight future trends in machine learning techniques for placement.

A Novel Reconfigurable Analog VLSI Architecture of M-point DFT Using Complex Matrix Multiplier and Graph-Based Signal Routing Method

A Novel Reconfigurable Analog VLSI Architecture of M-point DFT Using Complex Matrix Multiplier and Graph-Based Signal Routing Method

Load Based Dynamic Priority Arbiter for NoC Architecture

The evolution of Very Large Scale Integration (VLSI) and the semiconductor industry have led to the focus on multicore architectures. Network on Chip (NoC) is one of such arrangement which is an interconnection framework comprised of cores, routers, and links. The output port for each request from the input port must be computed, and the output channel must be reserved for the next router. However, the same output port can be requested by more than one input port, but only one request can be granted at a time. Multiple requests for a single output channel will lead to congestion of the packets, thereby increasing the network latency and leading to packet losses. The arbiter selects any one of the input ports and grants permission to use the requested output port while putting the other input port requests to wait. For a congestion-free traversal of packets and to avoid dropping of packets, a Load based Dynamic Priority Arbiter (LDPA) with dynamically changing priorities during run time based on the input port load has been proposed. The proposed customized arbiter LDPA works based on the updates made in the reservations of each input port. The priority of each input port is given according to the average load. More weight is allotted to the highly loaded input ports. By randomization, the chance is given to the lower priority input ports to reduce starvation and hence latency. With the use of the proposed LDPA, the average network latency is reduced by about 15.98% when compared to that of baseline FIFO arbiter, without any compromise in power and throughput.

Multi-Watt-Level 4.9-GHz Silicon Power Amplifier for Portable Thermoacoustic Imaging

Microwave-induced thermoacoustic (TA) imaging, combining high microwave contrast with high ultrasonic resolution has the potential to revolutionize applications such as continuous healthcare monitoring, point-of-care imaging, and biometric authentication. However, the size, cost, and integration of a high-power microwave transmitter is a key bottleneck in making TA imaging truly portable, affordable, and ubiquitous. Toward that end, this work presents a compact 4.9-GHz pulsed power amplifier (PA) with a 4.87-mm² active area implemented in a 55-nm BiCMOS technology, operating in a duty-cycled mode and achieving 37.3-dBm peak output power—the highest demonstrated peak power in PAs fabricated on a silicon substrate with deep submicron CMOS integration. We also reconstruct the first known high-fidelity TA images of tissue phantoms using an integrated silicon PA.

A Highly Reliable, Dynamic Logic-Based Hybrid MTJ/CMOS Magnetic Full Adder for High-Performance and Low-Power Application

At deep sub-micrometer technology, CMOS circuits suffer from high leakage and have reliability issues due to process variation. Hybrid magnetic tunnel junction (MTJ)/CMOS circuits have been proposed to overcome these challenges. MTJs have zero standby power and are compatible with CMOS technology. In this article, a dynamic logic-based hybrid MTJ/CMOS magnetic full adder (MFA) has been proposed, which eliminates the error voltage appearing on output due to charge injection and clock feedthrough phenomenon, thereby enhancing the performance of MFA and making it more reliable. This effect is induced by the pMOS transistor, which is used as a switch to precharge the output nodes. The proposed MFA uses two dummy transistors, whose drain and source terminals are shorted to make them act as MOS capacitors, to absorb the error voltage introduced by the switch pMOS transistor due to charge injection and clock feedthrough, when turned OFF. Eliminating the error induced due to charge injection and clock feedthrough makes the amplification process faster and reduces the dynamic power consumption. Results are verified by performing transient and Monte Carlo simulations using cadence virtuoso with UMC 40 nm CMOS technology kit and compact model of perpendicular magnetic anisotropy (PMA) MTJ, which validates that the proposed MFA is highly reliable as it provides the error-free output and imparts better power–delay product (PDP) compared to previously proposed MFA.

Physical Design of VCO with Wide Frequency Tuning Range Using Deep Submicron CMOS Technology

Abstract: This paper presents a new design approach of CMOS voltage controlled oscillator (VCO) with low power and wide frequency tuning range. A novel current starved delay cell has been proposed based on dual delay path architecture. The results have been obtained in 45 nm CMOS technology with supply voltage 1 V. The proposed VCO achieves a controllable frequency range from 1.81 GHz to 10.55 GHz with a wide tuning range. The control voltage (Vctrl) has been varied from 0.3V to 1V for obtaining the different output frequencies. The power dissipation of proposed VCO is 34.932 uW with current consumption as 0.079 mA at a control voltage of 1V and very optimised surface area as 14.8µm2. Keywords: Current starved delay cell, Low Power, Tuning range, VCO, etc.

A Low Power High Speed Accuracy Controllable Approximate Multiplier Design

Abstract: For energy effective and high performance design, the low power VLSI circuit is used. Multiplier is an essential part of low power VLSI design, since the effectiveness of the digital signal processor depends upon the multiplier. In multiplier circuit, utmost of the power is dissipated across in full adder circuits. Multiplication is one of the important process in microprocessor and there will be a lot of delay because of array multiplier, which can be compressed with the help of the column compressor approach. It uses a selection of half adders, full adders and compressors to sum the partial products in stages until two numbers are left. An 8 * 8 and 16 * 16 bit multiplier design is executed by assigning the adder and compressor. Partial product totality is the speed limiting operation in multiplication due to the propagation detention in adder networks. In order to reduce the propagation detention, compressors are introduced. Compressors calculate the sum and carry at each position concurrently. The attendant carry is added with a advanced significant sum bit in the coming stage. This is continued until the final product is generated. The partial product tree of the multiplier is estimated by the proposed tree compressor ( High Speed Compressor, Dual Stage Compressor, Exact Compressor). Keywords: Partial Products, Half Adder, Full Adder, High Speed Compressor, Dual Stage Compressor, Exact Compressor.

Power Reduction in 4T DRAM Cell Using Low Power Topologies

In today’s world there is a high demand in the development of VLSI circuits. The designers are paying attention to designing a good performance with zero hunger circuits in terms of power. At present, to design a high speed and a low cost device is becoming a major challenge for designers. In order to enlarge the demand of VLSI, CMOS technology plays a fundamental role. Dynamic Random Access Memory is the volatile memory, which is used in wide ranges of electronic based gadget applications. In this paper, the low power techniques like sleep transistor logic and Self Voltage Controllable Logic (SCVL) are implemented. A 4T DRAM cell using these low power logics has been designed and implemented. The power has been analyzed at 90nm technology. The simulation is done using the Tanner 13.1.EDA tool.

An Enhanced Memetic Algorithm using SKB tree representation for fixed-outline and temperature driven non-slicing floorplanning

Floorplanning is an ever-emerging field in the Very Large Scale Integration (VLSI) circuit design automation since it deals with essential design metrics of a floorplan, such as chip area, total wirelength, and temperature. This paper aims to optimize these design metrics to obtain an optimal floorplan with reduced computation time. A Skewed B* (SKB) tree based Enhanced Memetic Algorithm (EMA) is proposed for temperature-driven fixed-outline non-sliceable floorplanning. The proposed EMA has two search phases: a global search based on Genetic Algorithm (GA), and a local search based on the Adaptive Fast Simulated Annealing (AFSA) algorithm. A novel dynamic threshold bias search strategy is implemented to balance the search phases, thus increasing the convergence speed to obtain an optimal solution. The performance of the proposed algorithm is tested on MCNC (Microelectronic Centre for North Carolina), and GSRC (Gigascale System Research Centre) state-of-the-art benchmark circuits. Experimental results show that the EMA produces highly optimal design metrics on all tested benchmark circuits.

Pre-Silicon NBTI Delay-Aware Modeling of Network-on-Chip Router Microarchitecture

With enhancement of technology downscaling and packaging allows us to put more and more transistors within the same chip area. The Moore’s law still shows the growth in yield with increasing transistor density in deep sub-micron. This increment in transistor density encourages the computer architects to design Chip Multiprocessor (CMP) systems. In recent times, industry and researchers are focusing to add more cores per chip with increasing integration. The sharp growth in core numbers in System-on-Chip (SoC) raise intense challenges for communication among the cores. The scalability, fault tolerance and higher communication bandwidth features made Network-on-chip (NoC), a popular communication architecture than conventional bus architecture. However, the rapid shrinking of CMOS design margins in deep submicron technology has made aging mechanism such as Negative Bias Temperature Instability (NBTI), a prime concern in NoC design. In this paper, we propose a novel pre-silicon, NBTI stress aware circuit-to-system level solution for a reliable NoC router. To achieve reliability objective, we develop an NBTI aging-aware timing analysis framework based on the real workload stress. Our proposal is based on findings of most stressed path and cells due to NBTI induced effects. We develop an aging-aware cell library and used the multi Vdd technique to mitigate the NBTI induced delay effects. On the basis of volume of experimental analysis, we observed that 66.67% delay increases due to NBTI induced aging effects with real workload stress for a duration of five years. Our proposed NBTI stress mitigation algorithm and technique could able to reduce aging induced delay effects by 36%, hence enhancing the router performance under stress.

Design, integration and implementation of crypto cores in an SoC environment

PurposeThe paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations.Design/methodology/approachAn integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided.FindingsFPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm2 of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed.Originality/valueThe proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput.

Analyzing the Effect of Uncertainty in Low Power SRAM Cells Using Artificial Intelligence Technique

This paper addresses the uncertainty that is present in the design of static random access memory (SRAM) cells using an artificial intelligence (AI) technique. The SRAM has much uncertainty in high-performance portable very large-scale integration (VLSI) chips due to their performance and storage density. This paper presents the way for solving the uncertainty problem by evaluating point-by-point recreation derived for the memory cells inform of the power, speed, and area investment funds acquired in the advanced cell configuration when contrasted with the standard regular architecture for autonomous vehicles using AI algorithm. The adiabatic low power technique is implemented to enrich the configuration of the 6T-SRAM cells. The procedure of the adiabatic process will provide high loss in terms of dissipation of energy which is connected to ground (0V) and transition can be converted from ‘1’ to ‘0’. Moreover, this transition will be decreased to a high amount of degree within corresponding memory cells. Thus uncertainties with the AI model can able to deliver low power reduction using the automatic model of operation as standard adiabatic 6T SRAM cells are implemented. To prove the effectiveness in the reduction of uncertainties a low power margin is obtained with marginal values of 0.25 Volts which is much lesser than the existing models.