Novel Design of a Digital PLL for Power Reduction

Abstract

Very large-scale integration (VLSI) circuits operating at ultra-low power are currently acquiring more attention from the research group and the industries too. Recently, the performance of many applications depends on the size and energy consumption of sensor nodes. The energy efficient sensor nodes with reduced size are much preferred among applications such as wireless sensor networks, pollution and plant monitoring. The biggest challenge faced by the VLSI designers in present day life is designing a product of new generation which operates on minimum possible power. Power consideration is the eventual design criteria in different real-life applications like pacemakers etc. Phase Locked Loop is a framework that produces an output which is in phase with the input signal. In Phase Locked Loop (PLL), the focus is at the input signal’s phase with its output oscillator signal’s phase and thus modifies the recurrence frequency of the Voltage Controlled Oscillator (VCO) for phase co-ordination. The output signal from the Phase Frequency Detector is utilized to control the oscillator in a feedback circle also. As an operational gadget, the PLL has wide scope of utilization in media transmission, PCs and electronic applications. In this paper, designing and analysis of PLL with numerous outputs has been proposed to be implemented by changing the closed loop frequency control framework PLL blocks. As such, highly effective, low power, ideal area chip can be used for PLL with four various yields as PLL 8x, PLL 4x, PLL 2x and PLL 1x with different frequencies separately. Likewise, it is planned to utilize multi-threshold or sleep transistors to minimize the leakage current in the circuit. Further, the execution or performance verification of various parameters of PLL are done to acquire negligible power. Direct toolbox YALMIP is used as programming solver as an optimization tool. In addition to this, another method of Non- dominated sorting genetic algorithm (NSGA-II) Correlation for optimization is also introduced between both the strategies to find the best outcomes.