VLSI Research Articles

2023 IEEE Symposium on VLSI Technology and Circuits [Conference Reports

2023 IEEE Symposium on VLSI Technology and Circuits [Conference Reports

SSCS Kansai Chapter Technical Seminar, Special Reports on 2023 Symposium on VLSI Technology and Circuits [Chapters

SSCS Kansai Chapter Technical Seminar, Special Reports on 2023 Symposium on VLSI Technology and Circuits [Chapters

Crosstalk Peak Overshoot Analysis of VLSI Interconnects

As technology extended from deep sub-micron technology to nanometer regimes, the conventional copper (Cu) wire will not be able to continue. Now a substitute approaches such as Carbon Nano Tube (CNT) interconnects have been suggested to ignore the problems associated with global interconnects. Hence in this work, crosstalk analysis of Complementary metal oxide semiconductor (CMOS) buffer-driven of different interconnects have been analyzed for peak overshoot and overshoot width of Cu and CNTs for 16nm technology. For analyzing peak overshoot, the interconnect lengths are varied from 100um to 500um in 16 technology node for Cu, single walled carbon nanotube (SWCNT) and multi-walled carbon nanotube (MWCNT). The values of the peak overshoot and overshoot width changes, as the interconnect length increases, the peak overshoot and width is going to be increases. As Compared to Cu, SWCNT and MWCNT, the peak overshoot and width for SWCNT is lesser than copper and MWCNT. The MWCNT interconnect is less than that of conventional Copper interconnects.

Verification methods for complex-functional blocks in CAD for chips deep submicron design standards

The article discusses the design stages of very large-scale integrated circuits (VLSI) and the features of the procedure for verifying complex-functional VLSI blocks. The main approaches to microcircuit verification procedures are analyzed to minimize the duration of verification cycles. In practice, a combination of several approaches to verification is usually used.

Tunnel field effect transistor device structures: A comprehensive review

Downscaling of metal oxide semiconductor field effect transistors (MOSFET) has resulted in increased short channel effects (SCEs), off-leakage current and subthreshold swing. At room temperature, the minimum subthreshold swing for MOSFETs is 60 mV/dec. So, MOSFET is not suitable for the deep submicron regime. A new device structure is being investigated to overcome the limitations of MOSFETs. The tunnel field effect transistor is the new emerging device (TFET). TFETs are the most suitable candidate for low power applications due to their superior performance, such as low power dissipation, low leakage current, and subthreshold swing (SS) less than 60 mV/dec. Ambipolar effect is the main cause of high Ioff current, this effect can be reduced by the asymmetry in structure and varied doping in source and drain. As a result, the Ioff current in the TFET may be reduced and the Ion/Ioff current ratio can be increased. TFET is a simple p-i-n structure with reversed bias at the gate terminal and works on the principle of the band to band tunneling (BTBT). The basic structure of TFET also suffers from low Ion current. However, with the variation of physical parameters in structure, the Ion current can be improved. This paper reviews the physical parameters of TFET and their impact as well as different structures of TFET like surface tunnel transistors, p-i-n structure TFET, Junctionless TFET, and Dual gate TFETs, Heterojunction TFETs, Vertical TFETs, PNPN TFET, and Nanowire TFET.

Design and implementation of 10T-SRAM cell using Carbon Nano Tube Field Effect Transistor

SRAM is a key component in many VLSI circuits for efficient storage data. Various researches have been performed on implementation of SRAM using Conventional CMOS, FinFET and GNRFET technologies. But, these methodologies generating the more number of faults with high power and delay consumption, tosolve this problem proposed10T SRAM cell is implemented with the CNTFET respectively. Present research involving CNTFET SRAM deals with leakage analysis and dealt with the dual hilarity characteristics. Fault introduction and analysis of faults were limited with CMOS SRAM. The detection algorithms and circuits possess limitations in terms of detecting the current at nanoscales and restricted with CMOS SRAM. These limitations made us to pursue the research in these areas to bring novel ideas. The performance metrics evaluated and experimental analysis is made and it helps us to choose between various SRAMS. The simulation results shows that the proposed 10T SRAM consumes less delay and power compared to the 7T SRAM cell.

Implementation of Energy Effective Error Resistant Adders and Multipliers in Image Denoising Applications

The design of digital VLSI circuits must take energy efficiency into consideration. Reducing the circuit’s power consumption, which has been a major issue since 2000, would increase the necessity for energy efficiency. Error-tolerant systems heavily rely on approximate computation methods to increase power efficiency. The key factors of the system’s overall power consumption and area computation are adders and multipliers, which are also crucial in approximate computing. High energy-efficiency adders can be used to create additional multipliers. In order to dramatically minimize power consumption, this work builds and implements 8×8 Dadda multipliers using 1 bit approximation adders. Calculation is sped up by using the Dadda multiplier. In turn, by reducing propagation latency, the suggested design lowers power consumption in digital CMOS circuitry. The proposed multiplier design with approximate adders, which was created in Verilog HDL, simulated in FPGA, and synthesized in FPGA platform, is implemented on an ASIC platform using Cadence 90 nm Technology. The Gaussian filter additionally employs the proposed Dadda multiplier for picture denoising in approximation adder-based image processing applications.

IEEE SSCS/Electron Devices Society Bangladesh Joint Chapter Organizes “VLSI Design Competition 2022” [Chapters

To develop the semiconductor industry in any country, working knowledge of VLSI circuit design is crucial. To galvanize undergraduate students to learn and work in the burgeoning field of VLSI, a competition, “VLSI Design Competition 2022,” was jointly organized by the IEEE Solid-State Circuits Society (SSCS)/Electron Devices Society (EDS) Bangladesh Joint Chapter and the Department of Electrical and Electronic Engineering (EEE), Bangladesh University of Engineering and Technology (BUET). Neural Semiconductor Limited (NSL), one of the premier semiconductor companies in Bangladesh, sponsored the competition by providing financial and technical assistance.

Review on Low Power Alu Design Using Various Techniques

VLSI technology has advanced significantly, and there arenumerous effective methods for creating VLSI circuits. PTL, GDI(Gate Diffusion Input) methods, and CMOS are a few of the styles.The weaknesses of CMOS and PTL approaches can be eliminatedby using the GDI technique to create low-power digitalcombinatorial circuits. This method maintains a low level of logicdesign complexity while lowering the amount of power consumed,propagation latency, and size of digital circuits. This paper discussesthe benefits and limitations of GDI compared to CMOS design bycomparing the various approaches with respect to layout area,transistor count, latency, and power dissipation.

Review on multi bit flip-flop enhanced shift register: A low power solution for UART

This paper details the Verilog HDL- based design of UART modules. Developing UART with a shift register utilizing multibit flip-flops proves to be pragmatic strategy for contemporary VLSI circuits. This work supports not only asynchronous and serial communication but also aligns with essential objectives of minimizing power consumption and reducing overall circuit area. Such integration enhances data transmission efficiency while meeting crucial design considerations in modern electronics

A Novel Multicriteria Optimization Technique for VLSI Floorplanning Based on Hybridized Firefly and Ant Colony Systems

In VLSI circuit design, physical design is one of the main steps in placing the circuit into the chip area. Floorplanning is a crucial step in the physical design of IC design, which generates a blueprint for the placement of circuit modules into the chip. A floorplanning step accepts a netlist as its input, given by the circuit-partitioning step of physical design. The floorplanning step generates optimal placements for the circuit modules. The netlist contains the modules’ dimensions, size, and interconnect information. During the floorplan generation, the chip area, wire length required for connecting modules and the heat generated by the chips can be estimated. A good floorplan makes placements and routing simple. In order to improve the circuit performance by minimizing chip area, wire length, and peak temperature, it is essential to generate an optimized floorplan by developing metaheuristic optimization algorithms. A novel Hybridized Multicriteria Ant Colony and Firefly Optimization (HMAC-FO) technique is introduced to generate an optimized floorplan. The primary focus of HMAC-FO technique is to design a model for generating efficient floorplanning. The standard MCNC benchmark dataset has a number of modules with their connections. Firefly optimization is the main algorithm in HMAC-FO, which has been used in generating efficient floorplan with the optimized area, wire length and thermal. The firefly algorithm initially requires some number of solutions as the fireflies’ population. In the firefly algorithm, usually, the populations are generated randomly. But, to improve the firefly optimization algorithm’s performance and obtain better optimum results, the proposed technique uses ACO to generate the initial population, which are all optimal solutions. The firefly algorithm uses the set of optimal solutions as the initial population and generates the globally optimal result. The proposed technique has experimented with the standard MCNC benchmark circuits, and the results prove that the proposed algorithm reduces the area by 3.48%, the wire length by 0.64% and the temperature by 3.33% than the best existing methodology. The proposed methodology generates a good floorplan with all the required optimization, such as area, wire length and heat generation.

Data detection based on matrix decomposition for massive MIMO systems in realistic channel scenarios

Massive multiple-input multiple-output (MIMO) is a key technology for modern wireless communication systems. In massive MIMO receivers, data detection is a computationally expensive task. In this paper, we explore the performance and the computational complexity of matrix decomposition based detectors in realistic channel scenarios for different massive MIMO configurations. In addition, data detectors based on decomposition algorithms are compared to the approximate-inversion detection (AID) methods. It is shown that the alternating-direction-method-of-multipliers-based-Infinity-Norm (ADMIN) detection is promising in realistic channel environment and the performance is stable even when the ratio of the base-station (BS) antenna elements to the number of users is small. In addition, this paper studies the performance of several detectors in imperfect channel state information (CSI) and correlated channels. Our work provides valuable insights for massive MIMO systems and very large-scale integration (VLSI) designers to select the appropriate massive MIMO detector based on their specifications.

Asynchronous Circuit Principles and a Survey of Associated Design Tools

Planning and implementing a semiconductor integrated circuit is a highly complex process. Although physical limits seem to be approaching, it currently follows a growing evolutionary path. As deep submicron technologies evolve towards perhaps even sub-nano geometries, the design process complicates accordingly. Once subtle in higher geometry nodes, some effects become relevant or even dominant. Examples are effects that tamper the reliability of wires, such as crosstalk, or the adequate behaviour of gates, such as the increasing sensitivity to single event effects. Design techniques must thus also evolve, to provide a wide range of tools to deal with new effects during the integrated circuit design and test processes. This tutorial covers one set of design techniques that is often overlooked, but which can reveal themselves instrumental in dealing with the mentioned technology evolution, the use of clockless or asynchronous circuits. The tutorial is divided into three parts: first it introduces a metamodel for the digital circuit design process enabling to reason about distinct design styles; second, it covers the main principles of asynchronous circuit design, differentiating it from mainstream circuit design techniques such as conventional synchronous design; the third and last part presents a set of tools and systems that can be employed to effectively design asynchronous design, with emphasis on material that can be used to produce manufacturable circuits and systems, often associated to commercial integrated circuit synthesis, implementation and test tools and frameworks.

Reduction of variation and leakage in wide fan-in OR Logic domino gate

In this paper, a novel domino gate is proposed to decrease the process variability and leakage current with enhanced noise margin for wide fan-in OR logic. The process variation is decreased by reducing the transconductance of the keeper transistor, whereas the subthreshold leakage current is decreased by redesigning the evaluation network. In addition, a keeper-controlled network is developed to control the switching activity of keeper which eventually reduces the power dissipation. Further, extensive analysis of reliability is accomplished against the process, voltage, and temperature. Further, 64-word*32bit Read ported register file is designed to show the supremacy of proposed domino gate over the conventional domino. All proposed circuits are designed, simulated and verified using SPECTRE simulator in CADENCE VIRTUOSO at 45 nm CMOS technology node. The results reveal that power and delay variability are reduced by 55% and 57%, whereas noise margin is improved by 74% with respect to reported conventional domino. Hence, the analysis suggests that proposed domino circuit can be useful to implement deep submicron low power VLSI circuits.

Optimization of Power and Area Using VLSI Implementation of MAC Unit Based on Additive Multiply Module

The development of Digital Signal Processors (DSPs), graphical systems, Field Programmable Gate Arrays (FPGAs)/ Application-Specific Integrated Circuits (ASICs), and multimedia systems all rely heavily on digital circuits. The need for high-precision fixed-point or floating-point multipliers suitable for Very Large-Scale Integration (VLSI) implementation in high-speed DSP applications is developing rapidly. An integral part of any digital system is the multiplier. In digital systems as well as signal processing, the adder and multiplier seem to be the fundamental arithmetic units. Problems arise when using a multiplier in the realms of area, power, complexity, and speed. This paper details a more efficient MAC (Multiply- Accumulate) multiplier that has been tuned for space usage. The proposed design is more efficient, takes up less room, and has lower latency than conventional designs. The performance of the Additive Multiply Module (AMM) multiplier is measured against that of existing multipliers, where it serves as a module in the MAC reducing area and delay.

Characterization of Single Length Cycle Two-Attractor Cellular Automata Using Next-State Rule Minterm Transition Diagram

Cellular automata (CAs) are simple mathematical models that are effectively being used to analyze and understand the behavior of complex systems. Researchers from a wide range of fields are interested in CAs due to their potential for representing a variety of physical, natural and real-world phenomena. Three-neighborhood one-dimensional CAs, a special class of CAs, have been utilized to develop various applications in the field of very large-scale integration (VLSI) design, error-correcting codes, test pattern generation, cryptography and others. A thorough analysis of a three-neighborhood cellular automaton (CA) with two states per cell is presented in this paper. A graph-based tool called the next-state rule minterm transition diagram (NSRTD) is presented for analyzing the state transition behavior of CAs with fixed points. A linear time mechanism has been proposed for synthesizing a special class of irreversible CAs referred to as single length cycle two-attractor CAs (TACAs), having only two fixed points.

Особенности проектирования микросхем, выполненных по глубоко-субмикронным технологиям

Noise and signal integrity are important factors influencing the design process of microcircuits made using submicron technology. Currently, there is some difference in what design engineers can design and what can be manufactured with the right level of quality and reliability. Therefore, it is necessary to create a fundamentally new methodology for verifying VLSI projects with deep submicron design standards. In order to calculate the percentage of good chips manufactured, it is required to identify vulnerable effects and phenomena from the point of view of submicron technology. In this paper, the effect of noise on various types of microcircuits is studied and recommendations are given for limiting noise. One of the options for achieving the optimal balance between noise, noise immunity and microcircuit parameters is to add margins when calculating the VLSI parameters. The paper shows that VLSI projects with nanometer topological norms must undergo an additional process of verifying the parameters and functioning in general before issuing information for the production of photomasks. Verification requires the use of an integrated set of software tools that are certified in real production conditions.

Construction Technique and Evaluation of High Performance t-bit Burst Error Correcting Codes for Protecting MCUs

The occurrences of Multiple Cell Upset (MCU) are more liable to arise in modern memory systems with the continuous upgradation of microelectronics technology from micron to deep submicron scales. These MCUs are mainly induced due to radiations in memory systems. Error Correcting Codes (ECCs) with lower design complexity are generally preferred for the mitigation of MCUs. The major drawback of the existing ECC is requiring higher overheads as error correction capability increases. In this paper, authors have proposed a new class of high performance [Formula: see text]-bit Burst Error Correcting (BEC) codes. Parity check matrices ([Formula: see text]) have been proposed for 3-bit and 4-bit BEC codes with word lengths of 16-bit, 32-bit and 64-bit. Also a simplified decoding scheme has been introduced for these codes. The proposed codecs have been designed and implemented in FPGA and ASIC platforms. The proposed codecs are compact in area, faster in speed and efficient in power compared to existing related schemes. But these lower design constrains are achieved at the cost of increase in redundancy. So, the proposed codecs can be employed in applications where redundancy is not the only constrain for correcting [Formula: see text]-bit burst errors caused by MCUs.

A Method for Leakage Current and Power Reduction of Buffer in 65-nm CMOS Technology Based on the Pileup-Effect

In small-size Complementary Metal Oxide Semiconductor (CMOS) technology, the size of Very Large-Scale Integration (VLSI) below 90nm becomes higher and higher due to the enhancement of the short channel effect of transistors. CMOS Buffer is a very common circuit unit in VLSI. In this paper, a Pileup effect transistor (PET) is proposed to reduce the subthreshold leakage current of the CMOS buffer. The main principle of PET technology is to reduce the voltage difference between gate and source and the voltage difference between drain and source by lowering the voltage of source so as to reduce the subthreshold leakage current. Through simulation-based on Cadence and Taiwan Semiconductor Manufacturing Company (TSMC) N65 library, PET technology can reduce leakage current power consumption by about one-twelfth of the original while maintaining the function of the original CMOS buffer. PET technology has also been found to reduce current consumption in the transition state by about 40%.

Call for Applications and Nominations Search for the Editor-in-Chief of IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

Call for Applications and Nominations Search for the Editor-in-Chief of IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS