A Novel Multicriteria Optimization Technique for VLSI Floorplanning Based on Hybridized Firefly and Ant Colony Systems

Abstract

In VLSI circuit design, physical design is one of the main steps in placing the circuit into the chip area. Floorplanning is a crucial step in the physical design of IC design, which generates a blueprint for the placement of circuit modules into the chip. A floorplanning step accepts a netlist as its input, given by the circuit-partitioning step of physical design. The floorplanning step generates optimal placements for the circuit modules. The netlist contains the modules’ dimensions, size, and interconnect information. During the floorplan generation, the chip area, wire length required for connecting modules and the heat generated by the chips can be estimated. A good floorplan makes placements and routing simple. In order to improve the circuit performance by minimizing chip area, wire length, and peak temperature, it is essential to generate an optimized floorplan by developing metaheuristic optimization algorithms. A novel Hybridized Multicriteria Ant Colony and Firefly Optimization (HMAC-FO) technique is introduced to generate an optimized floorplan. The primary focus of HMAC-FO technique is to design a model for generating efficient floorplanning. The standard MCNC benchmark dataset has a number of modules with their connections. Firefly optimization is the main algorithm in HMAC-FO, which has been used in generating efficient floorplan with the optimized area, wire length and thermal. The firefly algorithm initially requires some number of solutions as the fireflies’ population. In the firefly algorithm, usually, the populations are generated randomly. But, to improve the firefly optimization algorithm’s performance and obtain better optimum results, the proposed technique uses ACO to generate the initial population, which are all optimal solutions. The firefly algorithm uses the set of optimal solutions as the initial population and generates the globally optimal result. The proposed technique has experimented with the standard MCNC benchmark circuits, and the results prove that the proposed algorithm reduces the area by 3.48%, the wire length by 0.64% and the temperature by 3.33% than the best existing methodology. The proposed methodology generates a good floorplan with all the required optimization, such as area, wire length and heat generation.