Very Large Scale Integration Design Research Articles

A Extensive Review of Recent Technologies and Trends in Low-Power VLSI Design

The demand for energy-efficient electronic devices has driven significant advancements in low-power Very-Large-Scale Integration (VLSI) design. This paper presents a Extensive review of the recent technologies and trends that have emerged to address the challenges associated with power utilization in VLSI circuits. The review covers a broad spectrum of innovations, including advanced transistor technologies such as FinFETs, Gate-All-Around (GAA) FETs, and Silicon-on-Insulator (SOI), which offer improved power efficiency. It also explores cutting-edge power enhance techniques like Dynamic Voltage and Frequency Scaling (DVFS), power gating, and Multi-Threshold CMOS (MTCMOS), highlighting their impact on reducing both dynamic and leakage power. Further, the paper examines energy-efficient architectures, including Near-Threshold Computing (NTC), approximate computing, and asynchronous circuits, which promise substantial power savings. The fusing of machine learning and AI in power optimization and the development of advanced Electronic Design Automation tools are also discussed as emerging trends. Finally, the paper considers future directions, including the potential of 3D Integrated Circuits (3D ICs), quantum and neuromorphic computing, and post-CMOS technologies, to revolutionize low-power VLSI design. This review provides a critical exploration of the actual state of the art and offers comprehensions into the future trajectory of low-power VLSI, making it a valuable resource for researchers and practitioners in the field.

Gamification for Teaching Integrated Circuit Processing in an Introductory VLSI Design Course

Gamification is being incorporated into university classrooms due to its educational benefits for students learning, including encouraging student behavior and engagement, and consequently improving learning outcomes. Despite gamification being increasingly used in education, little has been developed related to Very-Large-Scale Integration (VLSI). In this article, we describe two different gamification experiences applied to integrated circuit processing and design in an introductory VLSI design course for Electronic Engineers. While gamification in universities is still not very mature and our experience spans only two academic years, we observed that, with the practice of gamifying part of our course, the topics treated in games were profoundly learned and the experience was very positive in every aspect of the teaching–learning process.

Advancements in VLSI low-power design: Strategies and optimization techniques

As production technology advances, integrated circuits are increasing in size, leading to a corresponding rise in power consumption if not properly optimized. Consequently, the optimization of integrated circuit power consumption has gained paramount significance. This paper provides an overview of the theoretical and research developments in Very Large Scale Integration (VLSI) low-power design. Initially, the paper delves into the components of VLSI power consumption, elucidating the origins of various power consumption types and the factors influencing their magnitude. Subsequently, existing power reduction technologies are examined, including transistor-level optimization, gate-level optimization, and system-level power optimization. The principles, applicable power consumption types, as well as their respective advantages and drawbacks are analysed. The paper also introduces methods for evaluating VLSI power consumption and summarizes the characteristics, advantages, and disadvantages of high-level power estimation and low-level power estimation. Ultimately, it underscores the importance of considering multiple power optimization strategies during VLSI design and discusses research approaches for achieving low power consumption. This comprehensive exploration contributes to the enhancement and optimization of VLSI design efforts.

Review on Power Reduction Technology in VLSI Multiplier

As the demand for high-performance and energy-efficient integrated circuits continues to grow, power consumption in Very Large Scale Integration (VLSI) designs, especially in arithmetic units like multipliers, remains a critical concern. This paper presents a comprehensive review of various power reduction techniques employed in VLSI multipliers, highlighting recent advancements and key challenges in achieving lower power consumption. The review begins with an overview of the importance of power reduction in VLSI design and its impact on overall system performance. A significant portion of the paper is dedicated to circuit-level techniques, which are crucial for power reduction in VLSI multipliers. Furthermore, this review addresses the trade-offs between power reduction techniques and performance metrics such as speed and area utilization. It emphasizes the importance of carefully selecting the appropriate combination of techniques based on the specific application requirements.

Multi-Objective Genetic Algorithm-Based Technique for Achieving Low-Power VLSI Circuit Partition

Minimizing the power consumption of electronic systems is one of the most critical concerns in the design of integrated circuits for very large-scale integration (VLSI). Despite the reality that VLSI design is known for its compact size, low power, low price, excellent dependability, and high functionality, the design stage remains difficult to improve in terms of time and power. Several optimization algorithms have been designed to tackle the present issues in VLSI design. This study discusses a bi-objective optimization technique for circuit partitioning based on a genetic algorithm. The motivation for the proposed research is derived from the basic concept that, if some portions of a circuit's system are deactivated during the processor's idle time, the circuit's power consumption is automatically reduced. To reduce the overall system's power consumption, maximization of sleep time and minimization of net cuts are required. To achieve these, an effective fitness function has been constructed in such a way that the balance criteria are also maintained. The approach has been tested on a set of net lists from the ISPD'98 benchmark suite, each containing 10 to 30 nodes. The experimental results are compared with two existing methods that clearly indicate the acceptability of the suggested method. The suggested strategy achieves an average reduction of 24.69% and 31.46% for net cut, whereas average extensions of 15.20% and 12.31% are observed in sleep time when compared with two existing methods. The proposed method also achieves an average power efficiency of 14.98% and 12.09% with respect to these two state-of-the-art methods.

Boosting VLSI Design Flow Parameter Tuning with Random Embedding and Multi-objective Trust-region Bayesian Optimization

Modern very large-scale integration (VLSI) design requires the implementation of integrated circuits using electronic design automation (EDA) tools. Due to the complexity of EDA algorithms, there are numerous tool parameters that have imperative impacts on the chip design quality. Manual selection of parameter values is excessively laborious and constrained by experts’ experience. Due to the high complexity and lack of parallelization, most existing parameter tuning methods cannot make sufficient exploration in a large search space. In this article, we boost the efficiency and performance of parameter tuning with random embedding and multi-objective trust-region Bayesian optimization. Random embedding can effectively cut down the number of variables in the search process and thus reduce the runtime of Bayesian optimization. Multi-objective trust-region Bayesian optimization allows the algorithm to explore diverse solutions with excellent parallelism. Due to the ability to do more exploration in limited runtime, the proposed framework can achieve better performance than existing methods in our experiments.

A Very Large-Scale Integration Global Routing Optimization Model for Hybrid Physarum Bionetworks

Interconnection of billion transistors in a single layer of a die with the advent of the nanometer regime imposes a great challenge to handle the increased complexity, particularly in the global routing of the Very Large-Scale Integration (VLSI) physical design phase which involves distinct optimization in the computation of overall interconnect wire-length. In classical graph theory, the VLSI global routing problem can be mapped as a Rectilinear Steiner Minimal Tree (RSMT) Problem, which in itself is an NP-complete problem. The use of metaheuristics in solving this problem plays a major role where Ant Colony Optimization (ACO) and Particle Swarm Optimization (PSO) proved to be efficient algorithms. Both algorithms face certain limitations and inconsistencies in determining maximum optimization. A new optimization algorithm with insight from the biological activity of microorganisms has been proposed in this paper which is based on the behavior of the unicellular organism Physarum Polycephalum aiming at minimizing the wire length of VLSI interconnects. The paper further explores a new hybridization technique employing the use of Physarum BioNetwork and Particle Swarm Optimization together where PSO generate better possible Steiner’s in the initial stage for the final process using Physarum BioNetwork to ensure better convergence. Complexity analysis of the proposed algorithm has been performed and the simulation results achieved greater efficiency when compared with the conventional PSO algorithm and available industry benchmark over-optimizing Global Routing problem in VLSI design.

Progress on Memristor-Based Analog Logic Operation

There is always a need for low-power, area-efficient VLSI (Very Large-Scale Integration) design and this need is increasing day by day. However, conventional design methods based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) devices and Complementary Metal-Oxide-Semiconductor Transistor (CMOS) technology cannot meet the performance requirements. The memristor, as a promising computing and memory integration device, offers a new research idea for conventional logic circuit structure and architecture innovation, given its non-volatility, scalability, low power consumption, fast switching speed, etc. This paper proposes a brief overview of the characteristics and current status of memristor-based logic circuits and analyzes their applications in numerical expression and memory. The benefits and drawbacks of various analog logic circuit structures are summarized and compared. In addition, some solution strategies for these issues are presented. Finally, this paper offers prospects for the applications of memristors in the logic implementation of large-scale memristor arrays, the novel structure of in-memory computing, and neural network computing.

An Enhanced Deep Reinforcement Learning-Based Global Router for VLSI Design

Global routing is a crucial step in the design of Very Large-Scale Integration (VLSI) circuits. However, most of the existing methods are heuristic algorithms, which cannot conjointly optimize the subproblems of global routing, resulting in congestion and overflow. In response to this challenge, an enhanced Deep Reinforcement Learning- (DRL-) based global router has been proposed, which comprises the following effective strategies. First, to avoid the overestimation problem generated by Q -learning, the proposed global router adopts the Double Deep Q -Network (DDQN) model. The DDQN-based global router has better performance in wire length optimization and convergence. Second, to avoid the agent from learning redundant information, an action elimination method is added to the action selection part, which significantly enhances the convergence performance of the training process. Third, to avoid the unfair allocation problem of routing resources in serial training, concurrent training is proposed to enhance the routability. Fourth, to reduce wire length and disperse routing resources, a new reward function is proposed to guide the agent to learn better routing solutions regarding wire length and congestion standard deviation. Experimental results demonstrate that the proposed algorithm outperforms others in several important performance metrics, including wire length, convergence performance, routability, and congestion standard deviation. In conclusion, the proposed enhanced DRL-based global router is a promising approach for solving the global routing problem in VLSI design, which can achieve superior performance compared to the heuristic method and DRL-based global router.

Design and Testing of Digital Logic Gates Using HCS Macro-Model

Single Electron Transistor (SET) has become very popular in industry as well as in academia. As SET can control the tunneling of electrons one by one through the channel so that power dissipation is very low as compared to conventional Complementary Metal Oxide Semiconductor (CMOS), though it has high speed, high gain like properties. So, the hybridization of CMOS with SETcan be used in modern Very Large Scale Integration (VLSI) circuit design, and this technique is very popular as Hybrid CMOS–SET (HCS) which uses less power with high speed of response. But the model requires two distinct simulators, such as, Simulation Program with Integrated Circuit Emphasis (SPICE) for CMOS and SIMON or Korea Single Electron Circuit Simulator (KOSEC) or Monte Carlo Single Electronics Simulator (MOSEC) or Single-Electron Nano Electronic Circuit Analyzer (SENECA) for SET, to simulate a single HCS model. To overcome this problem of HCS, macro- modelling of SET has been introduced by different researchers which can be simulated by using MATLAB with SIMULINK, SPICE and so on. In this present paper, macro model of SET has been incorporated with CMOS so that it can be simulated using a single software and this technique has been used to develop different logic circuits and the output can be controlled by the individual components of SET macro model. The simulation results show that the proposed model also consumes low power (0.275 nW to 0.55 nW) with high speed which can be used in VLSI design.

VLSI Design Based on Block Truncation Coding for Real-Time Color Image Compression for IoT.

It has always been a major issue for a hospital to acquire real-time information about a patient in emergency situations. Because of this, this research presents a novel high-compression-ratio and real-time-process image compression very-large-scale integration (VLSI) design for image sensors in the Internet of Things (IoT). The design consists of a YEF transform, color sampling, block truncation coding (BTC), threshold optimization, sub-sampling, prediction, quantization, and Golomb-Rice coding. By using machine learning, different BTC parameters are trained to achieve the optimal solution given the parameters. Two optimal reconstruction values and bitmaps for each 4 × 4 block are achieved. An image is divided into 4 × 4 blocks by BTC for numerical conversion and removing inter-pixel redundancy. The sub-sampling, prediction, and quantization steps are performed to reduce redundant information. Finally, the value with a high probability will be coded using Golomb-Rice coding. The proposed algorithm has a higher compression ratio than traditional BTC-based image compression algorithms. Moreover, this research also proposes a real-time image compression chip design based on low-complexity and pipelined architecture by using TSMC 0.18 μm CMOS technology. The operating frequency of the chip can achieve 100 MHz. The core area and the number of logic gates are 598,880 μm2 and 56.3 K, respectively. In addition, this design achieves 50 frames per second, which is suitable for real-time CMOS image sensor compression.

A Review on low-Power VLSI CMOS and CNTFET Circuits

Nowadays, power consumption is one of the primary considerations in the design of VLSI (Very Large Scale Integration) circuits based on complementary metal oxide semiconductors (CMOS) and carbon nanotube field effect transistors (CNTFET). This is because of the present circumstance. The fundamental reason for this is that power utilisation has been raised to the status of a top priority due to the improvements in integration and scaling as well as the constant increases in operating frequency. Additional power consumption from circuits and designs makes them challenging to implement in portable devices. The quantity of power lost during operation has an immediate effect on the cost of packaging the IC and systems. A variety of power dissipation sources and low power VLSI design strategies for CMOS and CNTFET-based circuits are discussed in this article.

Performance analysis of Ternary Adder and Ternary Multiplier without using Encoders and Decoders

This work presents comparison of ternary combinational digital circuits that reduce energy consumption in low-power VLSI (Very Large Scale Integration) design. CNTFET and GNRFET-based ternary half adder (THA) and multiplier (TMUL) circuits has been designed using ternary unary operator circuits at 32nm technology node and implement two power supplies Vdd and Vdd/2 without using any ternary decoders, basic logic gates, or encoders to minimize the number of used transistors and improve the energy efficiency. The effect of CNTFET and GNRFET parametric variation with threshold voltage on performance metrics namely delay and power has been analyzed. Dependence of threshold voltage on the geometry of carbon nanotube and graphene nanoribbon makes it feasible to be used for ternary logic design. It is analyzed that CNTFET based circuits are energy efficient than the GNRFET- based circuits. It is also concluded that the CNTFET-based circuitshas less power-delay product (PDP) when compared to GNRFET- based circuits. CNTFET-based THA is 23.5% more efficient than GNRFET-based THA and CNTFET-based Tmul is97.8% more efficient than GNRFET-based Tmul.All the digital circuits have been simulated using HSPICE tool.

AI/ML/DL Algorithms and Applications in VLSI Design Technology Process Flow – A Brief Review

This paper gives a brief review of the AI/ML algorithms and applications that could be used in VLSI design technology. As the analysis and development of techniques that might lessen design complexity brought on by expanding process variability and shorten the turnaround time of chip manufacturing are clearly going to be a problem for the integrated circuit (IC) industry in the nanometre regime. The traditional approaches used for these activities are mostly manual, which takes time and resources. Contrarily, very large scale integration (VLSI) design and testing can take advantage of a variety of new automated ways thanks to the distinctive learning strategies of artificial intelligence (AI). Utilizing automated learning algorithms, AI and machine learning (ML) algorithms reduce the time and effort required to comprehend and process data within and across different abstraction levels, improving IC yield and speeding up production turnaround. This article examines the automated AI/ML methods for VLSI design and production that were previously used. The work presented in this paper is a technical seminar report of the P.G. (M.Tech) student, which is a part of the seminar that every student has to give w.r.t. any topic in the second semester of the PG programme.

A Survey of the Different Intelligent Algorithms for the VLSI-Based Design Flows for Various Embedded Applications in Electronics Engineering

The AI/ML applications and techniques that could be applied in VLSI design technology are briefly reviewed in this study. The integrated circuit (IC) industry will undoubtedly face challenges in the nano-meter regime related to the research and development of methods that could reduce design complexity brought on by increasing process variability and reducing the turnaround time of chip manufacture. The majority of the traditional methods utilized for these tasks involve manual labor, which requires time and resources. Contrarily, the unique learning strategies of artificial intelligence enable the design and testing of very large-scale integration (VLSI) to benefit from several innovative automated ways (AI). Artificial intelligence (AI) and machine learning (ML) algorithms use automated learning algorithms to reduce the time and effort needed to interpret and process data within and across different abstraction levels, enhancing IC yield and accelerating manufacturing turnaround. This article examines the formerly employed automated AI/ML methods for VLSI design and manufacture. The project that is the subject of this paper is a P.G. (M.Tech) student's technical seminar report, which is a component of the seminar that each student must deliver on any topic during the second semester of the PG program.

Recurrent deep neural learning classification algorithm based high level synthesis in VLSI circuit with runtime adaptability

Electronics industry has attained huge development in last few decades due to the rapid increase in system design applications. With the growth of very large scale integration (VLSI) design, integrated circuits (ICs) are employed in many applications. VLSI design comprises many steps like system-level design, high-level synthesis (HLS), logic design, test generation, and physical design. HLS interprets behavior description and create digital hardware that executes the behavior. But, the power-process-voltage-temperature (PPVT) variation can causee many issues and reduce the performance of VLSI design circuits. In order to address these problems, Recurrent Deep Neural Learning Classification based High Level Synthesis (RDNLC-HLS) Model is designed for better runtime adaptability with minimal time consumption. VLSI circuits are designed with the behavioral input and the output performance is measured at runtime. The behavioral description of the circuit is taken as input. Then, source code compilation process translates high level specification into Intermediate Representation (IR) and converts to control/data flow graph (CDFG). CDFG reveals data and control dependencies between operations. The proposed Recurrent Deep Neural Learning Classification based High Level Synthesis (RDNLC-HLS) Model is designed for providing better runtime adaptability with minimal time consumption. Finally, Register Transfer Level Generation is carried out to yield better runtime adaptability with minimal time. Simulation results on ISCAS’89 Benchmark Dataset, shows that the RDNLC-HLS model increases the FUSA with minimal error rate and CAT.

A Review on Low Power VLSI Design Models in Various Circuits

Low power design is one of the primary goals for any integrated circuits. Very Large-Scale Integration (VLSI) is a kind of Integrated Circuit (IC) that consists of hundreds and hundreds of transistor connection into a small chip. The communication and computer applications have grown very faster in the past decade due to the development of VLSI circuit design as microcontroller and microprocessors. However, still the research on VLSI are moving faster towards the scope of power and area minimization. The paper gives an overview about the recent methodologies that have been developed for the performance improvement of VLSI design and it shows the future directions of the areas that are to be concentrated on VLSI circuit design.

Novel Design of a Digital PLL for Power Reduction

Very large-scale integration (VLSI) circuits operating at ultra-low power are currently acquiring more attention from the research group and the industries too. Recently, the performance of many applications depends on the size and energy consumption of sensor nodes. The energy efficient sensor nodes with reduced size are much preferred among applications such as wireless sensor networks, pollution and plant monitoring. The biggest challenge faced by the VLSI designers in present day life is designing a product of new generation which operates on minimum possible power. Power consideration is the eventual design criteria in different real-life applications like pacemakers etc. Phase Locked Loop is a framework that produces an output which is in phase with the input signal. In Phase Locked Loop (PLL), the focus is at the input signal’s phase with its output oscillator signal’s phase and thus modifies the recurrence frequency of the Voltage Controlled Oscillator (VCO) for phase co-ordination. The output signal from the Phase Frequency Detector is utilized to control the oscillator in a feedback circle also. As an operational gadget, the PLL has wide scope of utilization in media transmission, PCs and electronic applications. In this paper, designing and analysis of PLL with numerous outputs has been proposed to be implemented by changing the closed loop frequency control framework PLL blocks. As such, highly effective, low power, ideal area chip can be used for PLL with four various yields as PLL 8x, PLL 4x, PLL 2x and PLL 1x with different frequencies separately. Likewise, it is planned to utilize multi-threshold or sleep transistors to minimize the leakage current in the circuit. Further, the execution or performance verification of various parameters of PLL are done to acquire negligible power. Direct toolbox YALMIP is used as programming solver as an optimization tool. In addition to this, another method of Non- dominated sorting genetic algorithm (NSGA-II) Correlation for optimization is also introduced between both the strategies to find the best outcomes.

LOW POWER VERY LARGE SCALE INTEGRATION (VLSI) DESIGN OF FINITE IMPULSE RESPONSE (FIR) FILTER FOR BIOMEDICAL IMAGING APPLICATION

Nowadays, the medical image processing techniques are using Very Large Scale Integrated (VLSI) designs for improving the availability and applicability. The digital filters are important module of Digital Signal Processing (DSP) based systems. Existing Finite Impulse Response (FIR) design approach performed with Partial Full Adder (PFA) based Carry Lookahead Adder (CLA) and parallel prefix adder logic in Vedic multiplier. Objective of this approach is to improve the performance of VLSI circuit by obtaining the result of area, power and delay, also, effective incorporation between VLSI circuit and image processing approach makes improved application availability. The design of high speed digital FIR filter is designed with various adders and multipliers. The incorporation of VLSI design and image processing techniques are used on biomedical imaging applications. The Enhanced FIR filter design utilized the hybrid adder and adaptive Vedic multiplier approaches for increasing the performance of VLSI part and the image processing results are taken from Matrix Laboratory tool. This proposed FIR filter design helps to perform the biomedical imaging techniques. The simulation result obtains the performance of enhanced FIR with area, delay and power; for biomedical imaging, Mean Square Error (MSE) and Peak Signal to Noise Ratio (PSNR) is obtained. Comparing with existing and proposed method, the proposed FIR filter for biomedical imaging application obtains the better result. Thus the design model states with various application availability of VLSI image processing approaches and it obtains the better performance results of both VLSI and image processing applications. Overall, the proposed system is designed by Xilinx ISE 14.5 and the synthesized result is done with ModelSim. Here the biomedical image performance is done by using MATLAB with the adaptation of 2018a. Keywords- Enhanced FIR filter; Adaptive vedic multiplier; Hybrid adder; Biomedical imaging; power delay product;

Design of Low Power and Failure Free SRAM Cell Using Read Assist Circuits

Static Random Access Memory (SRAM) is one of the main peripherals in all the Very-large-scale Integrated (VLSI) chips, which enact a vital part in all executable applications. The write ability and read stability are prime factors with low power supply and improve operation speed with temperature, process, and voltage variations. In VLSI design, the System on Chip (SoC) performance is improved by applying low power supply and change in few Pico seconds of cycle times or memory access. The read/write operation is not accurate in lower supply voltage because it will not flip to the desired voltage levels. For improving performance, proposed an SRAM cell to flip to the desired voltage levels to reduce readability failures in low supply voltages. The additional requirement is needed to increase the chip’s performance with lower supply voltages, and continuously additional circuit techniques are needed for obtaining the SRAM memory’s readability and writing ability. In this paper, different performance improvement methods of SRAM memory cells are analyzed. The reduced word line voltage read assist circuit is designed for the SRAM memory cell.