Vertical Nanowire FETs Research Articles

Effect of Quasi-One-Dimensional Properties on Source/Drain Contacts in Vertical Nanowire Field-Effect Transistors (VNWFETs).

In this study, we investigated the influence of quasi-one-dimensional (Quasi-1D) characteristics on the source and drain contact resistances within vertical nanowire (NW) field-effect transistors (FETs) of diminutive diameter. The top contact of the NW is segregated into two distinct regions: the first encompassing the upper surface, designated as the axial contact, and the second encircling the side surface, known as the radial contact, which is formed during the top-contact metal deposition process. Quantum confinement effects, prominent within Quasi-1D NWs, exert significant constraints on radial transport, consequently inducing a noticeable impact on contact resistance. Notably, in the radial direction, electron tunneling occurs only through quantized, discrete energy levels. Conversely, along the axial direction, electron tunneling freely traverses continuous energy levels. In a meticulous numerical analysis, these disparities in transport mechanisms unveiled that NWs with diameters below 30 nm exhibit a markedly higher radial contact resistance compared to their axial counterparts. Furthermore, an increase in the overlap length (less than 5 nm) contributes to a modest reduction in radial resistance; however, it remains consistently higher than the axial contact resistance.

Comparison of SiGeC/SiGe/SiC–Si heterojunction based vertical nanowire FET using non equilibrium Green's function

Advancement in FET technology has forced researchers to seek alternate semiconductor devices and materials. TFETs, junctionless FETs, and nanowires are a few examples of modern FETs, whereas Si alloys, graphene, and TMDC are a few materials that have shown promising behaviour to replace Si in the future. In this work, SiGeC/SiGe/SiC–Si based vertical heterostructure nanowires have been investigated. Due to the nanoscale dimensions of the FET and to incorporate the quantum effects along with Schrodinger-Poisson equations, non-equilibrium Green's function has been used as a principle simulator. For simulation, Ge/Carbon mole concentration of 0.25 and 0.01, respectively is used. To thoroughly investigate the effect of variation in doping profile and temperature range, simulated heterojunction nanowire showed that SiGeC-based nanowire result in a better ION/IOFF ratio as compared to SiGe and SiC-based heterojunction nanowire.

SkyBridge 2.0: A Fine-grained Vertical 3D-IC Technology for Future ICs

Gate-all-around field effect transistors (FETs) are set to replace FinFETs to enable continued miniaturization of ICs in the deep nanometer regime. IMEC and IRDS roadmaps project that 3D integration of gate-all-around FETs is a key path for the IC industry beyond 2024. In this article, we present SkyBridge 2.0, an IC technology featuring high density fine-grained 3D integration of vertical gate-all-around nanowire FETs, contacts, and interconnect while also solving 3D routability. We utilize industry-standard EDA tools to develop a customized design and technology co-optimization (DTCO) flow to design and evaluate SkyBridge 2.0. This DTCO flow covers process emulation of standard cells and SRAM to enable scalable manufacturing pathway, TCAD characterization of vertical nanowire FETs to obtain IV and CV characteristics, compact modeling accurately the device behavior, RC parasitic extraction of 3D interconnects and performance, and power and area assessment using ring oscillators. The technology assessment using ring oscillators shows that SkyBridge 2.0 at the chosen design point, using 10 nm nanowires, achieves ∼18% performance and 31% energy efficiency benefits compared to 7 nm FinFET technology. Area analysis of logic cells shows up to six times density benefits versus aggressively scaled 2D-CMOS cells. In addition to logic, we architect 3D SRAM to support low-power memory designs. SkyBridge 2.0 SRAM shows ∼20% improvement in read and write static noise margin, up to three times lower leakage current, and up to four times density benefits compared to 7 nm FinFET technology.

Benefits of using arrays of vertical nanowire FETs in integrated circuits to mitigate variability

We investigate the benefits of the use of arrays of vertical nanowire (vNW) field-effect transistors (FETs) to implement integrated circuits. By means of technology computer aided design and circuit simulations, the optimal dimensions of the vNWFETs are determined. Device and circuit variability levels have been investigated. The benefits of using array configurations are the decrease of the response time and a significant mitigation of the variability level as the number of the elements in the array increases.

(Invited) Impact of Processing Factors on the Low-Frequency Noise of Gate-All-Around Silicon Vertical Nanowire FETs

Future CMOS technology nodes will rely on Gate-All-Around (GAA) FETs with ultimate control over the short-channel effects. In this class of devices, GAA Vertical Nanowires (VNWs) offer some clear integration advantages over horizontal architectures. In addition, some operational parameters are also favourable, like, the low-frequency (LF) noise, as shown recently [1]-[3]. In this work, an overview will be given of the impact of certain processing factors on the noise spectrum and magnitude of silicon GAA VNW FETs.Silicon NWs with a diameter of ~45 (50) nm have been epitaxially grown on either bulk or Silicon-On-Insulator (SOI) substrates. They are either undoped (intrinsic) or in-situ B/P-doped (p/nMOS), resulting in the latter case in a Junctionless (JL) structure. For the “bulk” devices an in-situ B-doped (or P-doped) silicon back contact has been deposited as source electrode, while an in-situ B-doped SiGe source was grown on SOI (pFETs). In both cases, a highly B-doped SiGe (or P-doped silicon) drain was deposited on the 90 nm long NWs to reduce the series resistance. LF noise measurements have been performed as described elsewhere [1],[2], in linear operation (|VDS|=0.05 mV), for a current range from about 10 nA to a few mA. Spectra have been recorded in Forward (F) mode or in Reverse (R) mode, with source and drain switched.The impact of the width of the RMG cap, shown in Fig. 1 on the F noise of GAA VNW nFETs has been reported before [1], showing that the use of a wide cap results in a lower input-referred voltage noise PSD (SVG) (Fig. 2). The asymmetry in SVG at f=10 Hz in F and R operation of GAA VNW pFETs is represented in Fig. 3 (bulk source) and Fig. 4 (SOI). While significantly lower noise is observed in R operation for “bulk”, insignificant differences are seen for the SOI pFETs. At the same time, the PSD is generally lower for the bottom source (bulk) compared with a SiGe source on SOI (Fig. 5). More detailed analysis reveals that the 1/f noise is dominated by mobility fluctuations (Dm) for VNW pFETs on bulk substrates [2]. The situation is more complicated for SOI pFETs a shown in Fig. 6 and depends on the channel doping density. In weak inversion (low ID), either Dn or Dm fluctuations can prevail. At higher ID, access resistance (RS) starts to dominate the 1/f noise behaviour. Finally, also the in-situ B doping density plays a significant role in the LF noise mechanism of the JL channels (Fig. 6), offering several technology knobs to optimize the 1/f noise performance.[1] E. Simoen, A. Chasin, P. Matagne, E. Rosseel, A. Hikavyy, R. Loo, P. Favia, H. Bender, E. Vancoille and A. Veloso, ECS Trans., 97 (5), pp. 59-64 (2020).[2] E. Simoen et al., submitted to Solid-State Electron.[3] T. Imamoto, Y. Ma, M. Muraguchi and T. Endoh, Jpn. J. Appl. Phys., 54, p. 04DC11 (2015). Figure 1

(Invited) Impact of Processing Factors on the Low-Frequency Noise of Gate-All-Around Silicon Vertical Nanowire FETs

This paper gives an overview of the impact of certain processing steps on the low-frequency (LF) noise behavior of silicon Gate-All-Around (GAA) Vertical Nanowire (VNW) MOS transistors. It is shown that the width of a Replacement Metal Gate (RMG) cap impacts the flicker noise Power Spectral Density (PSD). The type of source contact, i.e., bulk versus a confined top contact significantly changes the nature and the magnitude of the 1/f noise. Finally, the doping density of the silicon nanowires has a subtle influence, whereby the dominant fluctuation mechanism shifts from number to mobility fluctuations, while increasing the doping density. Optimal noise performance is achieved for intermediate in-situ nanowire B doping density.

Compact modeling of 3D vertical junctionless gate-all-around silicon nanowire transistors towards 3D logic design

To sustain transistor scaling beyond lateral 7 nm devices, gate-all-around (GAA) junctionless vertical nanowire field effect transistors (JLNT) are one of the promising alternatives. To overcome the roadblocks of logic cell design using this emerging technology, this work explores compact modeling of 3D GAA-JLNTs based on physics of junctionless transport. The model features an explicit continuous analytical form of drain current calculations adapted for a 14 nm channel junctionless nanowire transistor (JLNT) technology and has been validated against extensive characterization results on a wide range of JLNT geometry, depicting good accuracy. Finally, preliminary simulations have been explored for performance assessment of logic circuits, such as inverters with passive load, active load and complementary topologies as well as ring oscillators, designed using the developed JLNT compact model.

Digital/Analog Performance Optimization of Vertical Nanowire FETs Using Machine Learning

Vertical nanowire field-effect transistors (NWFETs) have been optimized to maximize digital and analog performances using fully-calibrated TCAD and machine learning (ML) technique. Digital performance is quantified by RC delay ( $C_{gg}V_{dd}/I_{on}$ , where $C_{gg}$ is gate capacitance, $V_{dd}$ is operation voltage, and $I_{on}$ is on-state current) at the fixed off-state currents, and analog performance is quantified by the product of cut-off frequency ( $F_{t}$ ) and transconductance efficiency ( $G_{m}/I_{ds})$ . ML accurately predicted the geometry and doping parameters suggesting the best device performances. All the optimized NWFETs have larger drain diameters but smaller source diameters at the minimum of gate lengths, gate oxide thicknesses, drain junction gradients, and source/drain spacer lengths. Small source diameters are needed to tightly control the energy barrier to reduce the short-channel effects, whereas large drain diameters increase current drivability than $C_{gg}$ . Small drain junction gradients increase the lateral electric field from source to drain, which increases the carrier velocity. Longer spacer lengths decrease both $I_{on}$ and $C_{gg}$ , but the $I_{on}$ degradation is critical. These device characteristics validate the optimization results from ML, and ML-based optimization is fast and effective to maximize both digital and analog performances.

Investigation of device-circuit for negative capacitance vertical nanowire FETs based on SPICE model

In this study, a SPICE model for a negative capacitance vertical nanowire field-effect-transistor (NC VNW-FET) based on BSIM-CMG model and the Landau–Khalatnikov equation was presented. Suffering from the limitation of short gate length there is a lack of controllable and integrative structures for high performance NC VNW-FETs. A new kind of structure was proposed for NC VNW-FETs at sub-3 nm node. Moreover, in order to understand and improve NC VNW-FETs, the S-shaped polarization-voltage curve was divided into four regions and some new design rules were proposed. By using the SPICE model, device-circuit co-optimization was implemented. The co-design of gate work function and NC was investigated. A ring oscillator was simulated to analyze the circuit energy-delay, and it showed that significant energy reduction, up to 88%, at iso-delay for NC VNW-FETs at low supply voltage can be achieved. This study gives a credible method to analyze the performance of NC based devices and circuits and reveals the potential of NC VNW-FETs in low-power applications.

Opportunities and Challenges in Designing and Utilizing Vertical Nanowire FET (V-NWFET) Standard Cells for Beyond 5 nm

Nanowire field-effect transistors (NWFETs) are known to become the emerging transistor type for better performance and low power for future technology nodes beyond 7 nm. Their unique structures allow the transistors to be designed horizontally or vertically, leading to a smaller form factor. However, it is not well studied on how much improvements NWFETs can achieve, especially when vertical FETs (V-NWFETs) are invoked in designs. In this paper, we investigate the advantages that NWFETs provide to standard cell designs. We propose an interconnect structure and a design methodology that optimize design metrics such as area, wirelength, and capacitance of V-NWFET standard cells. Then, we perform comparisons on these design metrics to standard cells between FinFET, horizontal NWFET (H-NWFET), and V-NWFET. This study shows that H-NWFETs achieve significant capacitance reduction compared to the conventional FinFETs (-30.1%). In addition, V-NWFETs achieve even more capacitance reduction (-50.0%), and significant reduction in area (-22.5%) and wirelength (-14.4%) compared to FinFETs. This is possible because (1) fin-to-metal coupling consists of a significant portion in total capacitance and NWFETs contribute to the large reduction of this capacitance and (2) standard cells using V-NWFETs reduce significant area and wirelength compared to conventional FinFET standard cells. However, careful design and proper interconnect structure are required to fully exploit the design advantages.

Simulations of VNW-FETs with Adjustable Spacer-Like Negative Capacitors Based on Experimental Data

Vertical-nanowire-FETs (VNW-FETs) get a lot of attentions as promising devices in sub-5 nm nodes. Moreover negative capacitance (NC) is an emerging technique that can break through the lower limit of sub-threshold swings (SS) to reduce the power consumption of MOSFETs. However, suffering from the limitation of short gate length there is lack of controllable and integrative structures for high performance VNW-FETs with NC (NC VNW-FETs). In this study, a useful structure is proposed for NC VNW-FET, which can be used in high density ICs, and suitable for capacitance matching. To examine their performance, NC VNW-FETs were simulated by TCAD coupled with Landau-Khalatnikov ferroelectric equation of which the ferroelectric parameters were calibrated from our experimental HfZrO data. It's found that, for a certain ferroelectric layer thickness, when the NC area is larger than a critical area which is related to the Hf/Zr ratios and the thickness of ferroelectric layers, NC VNW-FET performance increases with the decreasing of NC area. Oppositely the NC VNW-FET is unstable when the NC area is smaller than the critical area. With the area optimized 9 nm Hf0.5Zr0.5O2 film, the Ion/Ioff ratio increases to 6 orders of magnitude and the minimum SS has reduced to 29.84 mV/decade.

Design and analysis of electrostatic-charge plasma based dopingless IGZO vertical nanowire FET for ammonia gas sensing

In this paper, Dopingless Gate All Around (GAA) Vertical Nanowire Field Effect Transistor (VNWFET) is designed with artificial material Indium Gallium Zinc Oxide (IGZO) as a channel material. IGZO channel has high electron mobility compared to more traditional amorphous semiconductors. In VNWFETs, since the channel length (Lch) is characterized vertically, it can be relaxed without area penalty on-chip, which in turn also allows some relaxation in the nanowire diameter while keeping optimum short-channel-effects control. Electrostatic-Charge Plasma technique is used to form a source-drain region on an intrinsic body of IGZO material. At the source side, the N+ region is formed by selecting the appropriate work function of the metal electrode, and at the drain side, the N+ region is formed by giving biasing to the metal electrode. N+ channel dopingless VNWFET with the catalytic metal gate is proposed for ammonia gas sensing. Cobalt, Molybdenum, and Ruthenium are used as a gate electrode in ammonia gas detection due to their high reactivity towards ammonia. Also, we have compared their ON and OFF sensitivity of the proposed device toward the gas adsorption. Due to the presence of gas on the gate, the metal work function of gate metal changes which varies the OFF-current (IOFF), ON-current (ION) and Threshold voltage (Vth) as these are considered as sensitivity parameters for sensing the ammonia gas molecules. The dimensional parameters (radius, and length) and dielectric materials are varied to check the change in device sensitivities. Results show that as the work function varies increases 50, 100, 150, 200 meV and 250 meV for catalytic metal at the gate, the sensitivity is increased.

(Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs

Over the past decades, aggressive and continuous transistor scaling according to Moore’s law has enabled new system features thanks to ever increasing device performance and density, reduced cost and power consumption. To keep the industry’s growth rate, triple-gate finFETs were recently implemented into manufacturing at the 22nm technology node [1]. These devices continue to be the subject of many innovations but face increasing scaling challenges for advanced (sub-)5nm nodes, with gate-all-around (GAA) nanowire (NW) FETs representing their ultimate scaling limit and being one of the most promising candidates to further support the CMOS roadmap (Fig. 1) [2-5]. In this work, we address some of the challenges faced by these 3D devices, focusing first on the impact of thermal and plasma treatments at gate module [6]. JG and noise can be substantially reduced, without EOT penalty, with a post HfO2 deposition anneal (PDA) and F incorporation in the gate stack by SF6. The latter can also improve the mobility and reduce Nit, mitigating the impact of fin patterning, fin corners and fin sidewalls crystal orientations, while also allowing a simplified dual-effective work-function (EWF) metal CMOS scheme where optimized cleans are key. PDA improves the bias-temperature-instability lifetime and hot-carrier immunity via reduction of bulk defects. Furthermore, the doping scheme and EWF metal can also be used to engineer the interface properties. Indeed, improved reliability and LF noise have been reported for junctionless (JL) GAA-NWFETs [4], with SVG.f of inversion-mode (IM) GAA-NWFETs showing more uniform oxide trap density profiles, as a function of depth, for TiAl-based vs. TiN EWF metals [7]. Extensionless IM or JL can also help to enlarge process robustness by ensuring a smaller Eox increase at the bottom-gate edges from the fins release process for lateral GAA-NWFETs formation [4]. These devices are closer to finFETs regarding layout and processing, but vertically stacked lateral NWs will be needed for them to be competitive in performance per footprint, with the drawback of increased parasitic capacitances [3]. Scaling is also being challenged as conventional 2D cell layouts are reaching the physical limits on gate and contact placement and facing interconnect routing congestion. Though requiring a more disruptive technological and design transition, vertical GAA-NWFETs appear particularly well placed to overcome some of these limitations and open up new scaling paths by fully using the third dimension [5]. Their gate length is defined vertically and hence can be relaxed without area penalty and used as a knob for variability control and optimized system performance. In this work, we tackle some of the integration challenges in surface definition for these devices, focusing on a channel-first approach. The vertical NWs (pillars) are defined by 193nm immersion lithography followed by dry-etch and wet treatments depending on the channel material employed. For NW doping, up to three stacked layers of (doped) epi are used, requiring pillar etch processes less sensitive to wide doping ranges. For Si NWs, using P doping for NMOS and B for PMOS, an optimized F-based plasma is used to yield arrays of high aspect-ratio pillars with diameters (dNWs) down to ~20nm (from ~42nm after litho). Further dNW reduction can be obtained by applying n cycles of low-temperature [O3-oxidation → oxide etch] for Si-based pillars, digital etch for III-V pillars [8]. Several alternative etch schemes are used for defining the layers surrounding the NWs, overcoming dry and wet etch-layout dependences. A replacement metal gate scheme can enable decoupling the gate module from doping/series resistance optimization for the top part of the pillars, where a highly doped epi layer can be grown for improved contacting (larger contact area). Removal of the dummy gate dielectric from the vertical channel is challenged by the presence of the layer(s) covering the top part of the pillars, selectivity requirements towards the bottom and top isolation layers, and, increasingly so for smaller dNWs, by metrology. A siconi-based oxide etch followed by a wet treatment is used prior to gate stack deposition, with a smoother gate electrode (with W fill-metal) easier to obtain than in a gate-first flow [5].

(Invited) Challenges on Surface Conditioning in 3D Device Architectures: Triple-Gate FinFETs, Gate-All-Around Lateral and Vertical Nanowire FETs

This work reports on some key integration aspects for 3D devices fabrication, focusing first on the impact of thermal and plasma treatments at gate module for triple-gate finFETs and their ultimate scaling limit: gate-all-around (GAA) nanowire (NW) FETs, which can be implemented in a lateral (with one or more lateral wires vertically stacked) or vertical configuration. The selected doping schemes and gate metals can also be powerful knobs to engineer the interface properties. In addition, specific steps for lateral NWFETs, such as the wires release process, will be addressed here. Vertical NWFETs, corresponding to the move from a 2D to a 3D CMOS layout, have the potential for lower parasitics, reduced power consumption and for enabling smaller, higher performing SRAM bitcells. We will present here alternative, novel approaches for building and characterizing these devices, focusing on channel-first schemes with improved process control, while tackling critical etch-layout dependences.

(Invited) Vertical Nanowire FET Integration and Device Aspects

This work reports on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer new, promising opportunities to enable further CMOS scaling and increased layout efficiency. Compared to triple-gate finFETs or lateral GAA-NWFETs, these devices are shown to have the potential for exhibiting lower parasitic RC and reduced power consumption at 5nm node design rules. They can also allow up to 30% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (Vmin), and lower standby leakage values. A comprehensive overview of some key integration aspects for VNWFET fabrication will also be addressed here, covering: VNW arrays, gate/top electrodes, and bottom/top isolation layers formation. In addition, we also present alternative solutions to obtain improved process control and to overcome etch-layout dependences which are especially critical within the context of vertical device integration using a channel-first approach.

(Invited) Vertical Nanowire FET Integration and Device Aspects

Over the past decades, aggressive and continuous transistor scaling according to Moore’s law has provided ever increasing device performance and density. For advanced (sub-)5nm nodes, to keep the growth pace, several options can be considered in terms of material choices, device architectures and circuits design. However, further cells scaling using conventional 2D layouts is becoming more and more challenged by key factors such as the physical limits on gate and contact placement and interconnect routing congestion. Vertical nanowire (VNW) devices appear particularly well placed to overcome some of these limitations, but require early process-design cross-disciplinary interactions to address the technological and design challenges/opportunities of moving from a 2D to a 3D layout configuration for CMOS. In this work, we will address some of these aspects, focusing first on a comparative analysis review of performance, parasitics and layout efficiency between VNWFETs (3D layout) and lateral nanowire (LNW) FETs or finFETs (2D layout), followed by a comprehensive overview of some key integration aspects regarding VNWFET devices fabrication. In VNWFETs, since the gate length (Lgate) is defined vertically, it can be relaxed without area penalty, which in turn also allows some relaxation in the NW diameter, while keeping optimum short-channel-effects control. This is an important advantage of the vertical device architecture as several theoretical studies predict mobility degradation below a certain NW dimension, which would also cancel off the gains of using high-mobility channels such as Ge or III-V over silicon [1,2]. Moreover, Lgate relaxation is an important knob for variability optimization and leakage control, critical in scaled SRAMs. In terms of layout, VNWFETs can enable more compact cells [2,3], for instance by placing two pull-up transistors on the same row of a SRAM cell, saving around 30% area in comparison to a finFET-based SRAM [2]. A comparative simulation analysis in [4] of NAND library cells also suggests promising speed gains and power consumption reduction when switching from a 7nm Si-baseline finFET technology to 5nm Si VNWFETs. In addition, despite their potential for lower parasitic RC, VNWFETs asymmetry for source/drain wiring needs to be taken into account in circuit design and in processing for bottom access resistance optimization [2,5]. From an integration perspective, two main routes can be considered for device fabrication: channel-first or channel-last. In this work, we will focus on the first approach for added flexibility in terms of channel material choice [Si, (Si)Ge, III-V] and also control of the channel (defects) quality. Channel body (NW pillar) definition is done using 193nm immersion lithography followed by dry-etch. For the particular case of III-V, a bottom-up approach can also be considered for the NWs growth [6] (Fig.1). NW diameter (CD) shrinkage by dry-etch is challenged by the local CD uniformity control of the pillars within the NW arrays and their high aspect-ratio. Further CD reduction, and potentially also smoothening of the NW sidewalls, can be obtained by applying n cycles of low-temperature, [O3-oxidation -> oxide etch] for Si-based pillars, digital etch for III-V pillars [7]. With regards to Si NW doping, for simplicity in terms of junction formation, we rely on growing up to three stacked layers of (uniformly doped) Si epi. A wide doping range for a given layer and a sharp doping concentration steepness between doped regions are feasible via tuning of the growth conditions such as pressure and B2H6 flow (for B-doped Si epi, PMOS). For extra simplicity, junctionless type of devices can also be particularly interesting to consider as they do not require junctions [8]. In a vertical device flow, control of the thickness of the different layers surrounding the NW pillars is key (Fig.2), both for a gate-first or a gate-last scheme, the latter enabling further options for device fabrication such as decoupling the gate module from doping/series resistance optimization for the top part of the NW. Here, layout dependences observed for several dry and wet etch processes and specific etch-back challenges (e.g., W surface roughness control) triggered the need for introduction of alternative schemes for improved process control of the layers on the wafers.

Benchmarking of MoS2FETs With Multigate Si-FET Options for 5 nm and Beyond

In this paper, we benchmark the performance of monolayer and bilayer MoS2 FETs (MFETs) against various multigate (MuG) Si-FET options, such as FinFETs and lateral and vertical nanowire FETs, for a 5-nm node and beyond. We compare the performance metrics of all the device options at the ring-oscillator (RO) level, accounting for not only intrinsic and extrinsic parasitic elements but also interconnects. Using the atomistic two-band ballistic quantum transport simulations, we evaluate ON-current and intrinsic capacitances for MoS2-based devices. Furthermore, we calibrate two-band model currents with more sophisticated full-band diffusive simulations to obtain realistic performance metrics at the circuit level. We show that both the intrinsic and parasitic capacitances of a single-gate MFET are lesser than those of a double-gate (DG) MFET, resulting in 13% lesser energy consumption. A DG bilayer (DGBL) MFET shows the best performance among different MFETs. In comparison toMuG FETs, the DGBL MFET offers not only lower energy consumption but also 35%–45% lower speed. In the end, to meet the target performance, we evaluate the impact of the device current, contact resistance, and back-end-of-the-line load on the speed of RO with the DGBL MFET.

Ambient field effects on the current-voltage characteristics of nanowire field effect transistors

We investigate the effects of ambient field from the gate and drain contacts on the current-voltage characteristics of a vertical nanowire field effect transistor having a lightly doped ungated length near the drain. Such a device is suitable for high voltage (tens of volts) applications. It is shown that the ambient field enhances the carrier concentration and divides the ungated region into gate-controlled and drain-controlled sections, controllable by the drain contact size and bias-voltages. These phenomena have a significant impact on the drain breakdown voltage, saturation voltage, saturation current and output resistance. The effects are established with the help of measured data and numerically calculated current-voltage curves and field lines.

Vertical Nanowire Field Effect Transistor in the Flexible Polymer Foils Based on Ion Tracks

Fabrication of flexible device structures and nanoscale size definition are presently among the most important and ambitious development goals in the IT field. We have recently prepared the vertical nanowire field effect transistor in the flexible polymer foils based on ion tracks. The high-energetic fast heavy ions were used to irradiate the 8μm PET foils and then the chemical etching method were employed to prepare cylindrical channels in these PET foils. These channels were subsequently filled with insulator material and semiconductor, and then provided with suitable metallic contacts, to obtain a vertical field-effect transistor device. Preparation and first electronic results on this new device are reported. Typically over 107 transistors per cm2 with the devices’ diameter of ~100 nm can be obtained in this technique. The fabrication does not require lithography on the scale of a single transistor, and is suitable for large-area and flexible applications.

Vertical nanowire transistor in flexible polymer foil

Fabrication and operation of a vertical nanowire field-effect transistor is reported. The device is prepared by growing vertical wires in the cylindrical pores of a polymer foil stack. The nanowire diameter is approximately 100 nm, the packing density up to 108 cm−2. The polymer foil stack consists of two polymer layers and an intermediate metal layer. Cylindrical holes are prepared in this stack by using fast ion irradiation and subsequent etching. Well-defined cylindrical openings with diameters between 50 and 150 nm are obtained. The semiconductor growth involves electrodeposition of the p-type quaternary compound CuSCN. Electrical measurements on first devices show transistor action with some gate leakage, which may be improved in future designs. The arrangement of inorganic device material embedded in soft polymer matrix is structurally robust, and the devices show low sensitivity to mechanical strain of the foil. Single electron effects may be expected in these devices, when the dimensions are further reduced.