Simulations of VNW-FETs with Adjustable Spacer-Like Negative Capacitors Based on Experimental Data

Abstract

Vertical-nanowire-FETs (VNW-FETs) get a lot of attentions as promising devices in sub-5 nm nodes. Moreover negative capacitance (NC) is an emerging technique that can break through the lower limit of sub-threshold swings (SS) to reduce the power consumption of MOSFETs. However, suffering from the limitation of short gate length there is lack of controllable and integrative structures for high performance VNW-FETs with NC (NC VNW-FETs). In this study, a useful structure is proposed for NC VNW-FET, which can be used in high density ICs, and suitable for capacitance matching. To examine their performance, NC VNW-FETs were simulated by TCAD coupled with Landau-Khalatnikov ferroelectric equation of which the ferroelectric parameters were calibrated from our experimental HfZrO data. It's found that, for a certain ferroelectric layer thickness, when the NC area is larger than a critical area which is related to the Hf/Zr ratios and the thickness of ferroelectric layers, NC VNW-FET performance increases with the decreasing of NC area. Oppositely the NC VNW-FET is unstable when the NC area is smaller than the critical area. With the area optimized 9 nm Hf0.5Zr0.5O2 film, the Ion/Ioff ratio increases to 6 orders of magnitude and the minimum SS has reduced to 29.84 mV/decade.