Vertical Hall Devices Research Articles

Integrated three-dimensional Hall switch sensor based on independent optimized Hall devices

This paper presents an integrated 3D Hall switch sensor with a 100 kHz signal bandwidth, which can detect three-dimensional (3D) magnetic field and output digital signals. 3D magnetic field detection relies on the integration of the horizontal Hall devices (HHD) and vertical Hall devices (VHD), and usually requires the performance of HHD and VHD to match each other. Therefore, an independent optimization method is applied to 3D Hall sensor to realize the matching between HHD and VHD. This method allows the doping concentration and doping profiles of VHD can be designed different from HHD. The simulation results show that the optimized HHD can achieve a voltage sensitivity SV of about 20mV/VT and a residual offset of 20 μV at a 3.3 V supply voltage, while VHD are optimized independently for SV up to 20mV/VT, and the residual offset is less than 100 μV after applying offset cancellation technology. In addition, in order to reduce the power consumption and area of the Hall sensor, the Hall signal processing circuit adopts the time-division multiplexing method to realize the detection of the 3D magnetic field in one working period. During the working period, the circuit uses logic control timing circuit to realize wake-up and sleep mode, which further effectively reduces the overall power consumption of the sensor. The Hall sensor chip has been fabricated in 0.18 μm CMOS technology with an area of 1.46 mm2. The measured results show the power consumption of the chip in the Z-axis direction is about 11.88 mW in the wake-up mode and only 49 μW in the sleep mode, at a 3.3 V supply voltage.

Investigation of the Sensitivity of a Novel Vertical Hall Device Based on the Buried Layer

This article proposes a novel five-contact vertical Hall device (VHD) with a buried layer (BL-5CVHD) compatible with a standard bipolar-CMOS-DMOS (BCD) process. VHDs sense a parallel magnetic field. Therefore, the transverse currents in the active region of VHDs determine the magnetic sensitivity. The BL provides a longitudinal electric field for majority carriers to form a transverse current, improving sensitivity. Through dedicated numerical simulations, we observe that the BL leads to a symmetrical distribution of the Hall potential, presenting better transverse currents. The geometric parameters of the BL-5CVHD are then further analyzed and optimized. Ultimately, the optimized BL-5CVHD voltage-related sensitivity reaches 10.53% <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{T}^{-{1}}$ </tex-math></inline-formula> . Meanwhile, the offset voltage decreases to 0.55 mV.

An integrated front-end vertical hall magnetic sensor fabricated in 0.18 μm low-voltage CMOS technology

An integrated front-end vertical CMOS Hall magnetic sensor is proposed for the in-plane magnetic field measurement. To improve the magnetic sensitivity and to obtain low offset, a fully symmetric vertical Hall device (FSVHD) has been optimized with a minimum size design. A new four-phase spinning current modulation associated with a correlated double sampling (CDS) demodulation technique has been further applied to compensate for the offset and also to provide a linear Hall output voltage. The vertical Hall sensor chip has been manufactured in a 0.18 μm low-voltage CMOS technology and it occupies an area of 1.54 mm2. The experimental results show in the magnetic field range from –200 to 200 mT, the entire vertical Hall sensor performs with the linearity of 99.9% and the system magnetic sensitivity of 1.22 V/T and the residual offset of 60 μT. Meanwhile, it consumes 4.5 mW at a 3.3 V supply voltage. The proposed vertical Hall sensor is very suitable for the low-cost system-on-chip (SOC) implementation of 2D or 3D magnetic microsystems.

Simulations of residual offset of Five-Contact vertical Hall devices with slim waist

As an important part of three-dimensional (3D) magnetic sensors, the vertical Hall devices directly determine the overall performance of the sensors. However, the traditional vertical Hall devices (5CVHD) have large offset and low sensitivity due to an inherent electrical asymmetry. In order to solve this problem, the traditional five-contact vertical Hall devices are optimized to obtain the five-contact vertical Hall devices with slim waist (SW-5CVHD) in this paper, and an anti-parallel coupling method which is suitable for the devices is applied. In addition, based on TCAD software, this paper gives a new 3D process simulation model that is more accurate than the traditional 2D model. The 3D simulation results show that the SW-5CVHD have higher sensitivity and lower initial offset compared to the traditional 5CVHD. After applying the anti-parallel coupling method, the novel devices achieve a higher symmetry by double identical SW-5CVHD interconnected into what we call the anti-parallel coupling double SW-5CVHD (APSW-5CVHD). As the structure of APSW-5CVHD is fully symmetrical, which can be better combined with the spinning current technology for offset cancellation. As a simulation result, with a bias voltage of 1 V and after spinning current a mean equivalent residual offset of 60.0µT with a standard deviation of 74.4µT is achieved among 15 samples. Moreover, the Hall voltage sensitivity is approximately 21.7 mV/VT at 1 V bias voltage.

Sensitivity Improvement of a Fully Symmetric Vertical Hall Device Fabricated in 0.18 μm Low-Voltage CMOS Technology

This paper proposes a new implementation method to significantly improve the magnetic sensitivity of a fully symmetric vertical Hall device (FSVHD) based on low-voltage CMOS technology. The FSVHD consists of four identical three-contact vertical Hall elements (3CVHE) and each 3CVHE is located in a low-doped deep n-well. The terminals of the 3CVHE are $\text{n}^{+}$ implanted in an n-well and a $\text{p}^{+}$ implantation in a p-well is performed to act as a trench between two adjacent $\text{n}^{+}$ contacts, enabling Hall current flowing deeply for sensitivity improvement. The influence of the geometry sizes on magnetic sensitivity is exploited utilizing TCAD simulation to obtain the optimized device structure in a $0.18~\mu\text{m}$ CMOS standard technology. The experimental results reveal that the proposed FSVHD with a $\text{p}^{+}$ /p-well trench can attain an improved voltage-related sensitivity of 8.4 mV/VT, which is about 70% higher than that of a conventional FSVHD without a trench in the same CMOS fabrication process, while offset and noise are not degraded. The proposed $\text{p}^{+}$ /p-well implantation trench is a good solution to enhance the sensitivity of a low-voltage CMOS VHD with a low manufacturing cost.

Drift of the sensitive direction of Hall-effect devices in (1 0 0)-silicon caused by mechanical shear stress

Conventional Hall effect devices are designed to respond to a single magnetic field component in 3D space. However, if plastic encapsulated Hall effect devices in cubic crystals are exposed to poorly defined and unstable mechanical shear stress, small portions of unwanted, perpendicular magnetic field components will show up in the Hall output signals. Mathematically, any such crosstalk – may it originate from mechanical stress or not – can be expressed as a Taylor series in powers of the magnetic field. The even powers are the well known planar Hall effect at zero mechanical stress. In practice powers of even order are irrelevant, because they are eliminated by the widely used spinning current schemes. In this paper we address the odd powers of the magnetic crosstalk and their drift versus mechanical stress. The effect is small for Hall plates but large for Vertical Hall devices in (100)-silicon. It is fully described by piezo-resistance and piezo-Hall tensors. We present results of numerical simulations and measurements. Thin devices are less affected than thick devices. If magnetic angle sensors are made of Vertical Hall devices, in-plane shear stress leads to small orthogonality errors. This article lays the foundations for compensation circuits to eliminate such shear-stress induced orthogonality errors.

Design and Simulation of Novel Low-Voltage CMOS Vertical Hall Devices With Capacitively Coupled Measuring Contacts

In this article, we introduce the novel concept of capacitively coupled measuring contacts (CCMCs) for microscaled vertical Hall sensors. Using dedicated numerical simulations, we show how this concept results in shaping and consequent focusing of the Hall potential into the measuring contacts and, in addition, strongly reduces the parasitic short-circuit current flowing into the measuring contacts. We use these effects purposefully for the design of novel low-voltage CMOS vertical Hall sensors with high magnetic sensitivity. The shallow well along with the CCMCs confines the sensor response to a small active region, which shows potential for a wide range of applications.

Basic relationships for Hall half-plane structures with multiple extended contacts on the boundary: Applications to the extraction of physical parameters and optimization of graphene and vertical Hall devices

The basic relationships for a Hall plate with N non-symmetric contacts placed in an arbitrary magnetic field are a set of N-1 relationships that are necessary and sufficient for the existence of a complex electrostatic potential function. By the application of the boundary conditions, they turn into a linear system of N-1 compatibility conditions involving the terminal voltages and currents. The construction of the basic relationships requires the positions of the contact extremities on the real axis of the canonical domain (the upper half-plane) as well as the electric and magnetic parameters of the Hall device. The conduction and resistance matrices can be obtained easily from the basic relationships. They give an effective method for predicting the performance of both horizontal and vertical Hall effect devices and provide a useful method for designing these types of planar devices.

Analysis of Orthogonal Coupling Structure Based on Double Three-Contact Vertical Hall Device.

A vertical Hall device is an important component of 3D Hall sensors, used for detecting magnetic fields parallel to the sensor surface. The Hall devices described in existing research still have problems, such as large offset voltage and low sensitivity. Aiming to solve these problems, this study proposes a double three-contact vertical Hall device with low offset voltage, and a conformal mapping analysis method to improve the sensitivity of the device. Secondly, an orthogonal coupling structure composed of two sets of double three-contact vertical Hall devices is proposed, which further reduces the offset voltage of the device. Finally, the TCAD simulation software was used to analyze the performance of the devices, and an existing vertical Hall device was compared to ours. The results show that the orthogonal coupling structure in this study exhibits better performance, reaching an average voltage sensitivity of 17.5222 mV/VT and an average offset voltage of about 0.075 mV. In addition, the structure has the same magnitude of offset voltage in the four phases of the rotating current method. This characteristic enables the back-end circuit to more accurately filter out the offset voltage and acquire the Hall signal.

A New Design of a Single-Device 3D Hall Sensor: Cross-Shaped 3D Hall Sensor.

In this paper, a new single-device three-dimensional (3D) Hall sensor called a cross-shaped 3D Hall device is designed based on the five-contact vertical Hall device. Some of the device parameters are based on 0.18 μm BCDliteTM technology provided by GLOBALFOUNDRIES. Two-dimensional (2D) and 3D finite element models implemented in COMSOL are applied to understand the device behavior under a constant magnetic field. Besides this, the influence of the sensing contacts, active region’s depth, and P-type layers are taken into account by analyzing the distribution of the voltage along the top edge and the current density inside the devices. Due to the short-circuiting effect, the sensing contacts lead to degradation in sensitivities. The P-type layers and a deeper active region in turn are responsible for the improvement of sensitivities. To distinguish the P-type layer from the active region which plays the dominant role in reducing the short-circuiting effect, the current-related sensitivity of the top edge (Stop) is defined. It is found that the short-circuiting effect fades as the depth of the active region grows. Despite the P-type layers, the behavior changes a little. When the depth of the active region is 7 μm and the thickness of the P-type layers is 3 μm, the sensitivities in the x, y, and z directions can reach 91.70 V/AT, 92.36 V/AT, and 87.10 V/AT, respectively.

Performance prediction of four-contact vertical Hall-devices using a conformal mapping technique**Project supported by the Natural Science Foundation of Jiangsu Province, China (Nos. BK20131379, BK20141431) and the Graduate Research and Innovation Projects of Jiangsu Province (No. SJLX_0373).

Instead of the conventional design with five contacts in the sensor active area, innovative vertical Hall devices (VHDs) with four contacts and six contacts are asymmetrical in structural design but symmetrical in the current flow that can be well fit for the spinning current technique for offset elimination. In this article, a conformal mapping calculation method is used to predict the performance of asymmetrical VHD embedded in a deep n-well with four contacts. Furthermore, to make the calculation more accurate, the junction field effect is also involved into the conformal mapping method. The error between calculated and simulated results is less than 5% for the current-related sensitivity, and approximately 13% for the voltage-related sensitivity. This proves that such calculations can be used to predict the optimal structure of the vertical Hall-devices.

A Compact Behavioral Simulation Model for CMOS Vertical Hall-Effect Devices

A compact behavioral simulation model for CMOS five-contact vertical Hall devices is presented. In term of the internal current flow geometry, the vertical Hall device is modeled based on an asymmetric Wheatstone bridge structure, including four current-controlled Hall voltage sources and four asymmetric lumped resistors. The lumped resistors on the Wheatstone bridge are calculated preliminarily by conformal mapping method. More importantly, the model takes into account the lateral diffusion effect and junction field effect which further improves the simulation accuracy. The behavioral model has been written in Verilog-A language with ten more physical and process parameters. The behavioral model simulation has been successfully performed in the Cadence Spectre environment with 0.8 μm high voltage CMOS technology parameters. The model’s simulation results are in good agreement with the reported experimental results.

Improved Magnetic Sensitivity of CMOS Vertical Hall Device by Using Partial Implantation Technique

With the continuous scaling of CMOS technology, the doping level of N-well is constantly increasing, which leads to a big decrease in magnetic sensitivity for vertical Hall devices (VHDs). Moreover, the Gaussian profile of doping concentration gives an additional decrease in N-well effective depth, which further reduces the magnetic sensitivity. In this paper, we apply partial N-well and top p+ layer implantation techniques to lower the doping level of N-well and improve the doping profile by means of impurity lateral diffusion and compensation effects. TCAD process and device simulations have been carried out for a typical five-contact VHD in 0.13 μm CMOS technology. Simulation results show that the current-related magnetic sensitivity is greatly improved from 40 V/AT to 110 V/AT by using the partial implantation techniques. Meanwhile, the voltage-related magnetic sensitivity is also increased and not significantly decreased.

Compact modeling of vertical hall-effect devices: electrical behavior

This paper presents the development of a design-oriented compact model of vertical Hall-effect sensors integrated in CMOS technologies. Such a model makes easier the design of integrated Hall systems, permitting designers to co-simulate the Hall sensing element with the biasing and processing electronics thanks to a single electrical simulator. Here focus is put on the electrical behavior, i.e. the resistive behavior of a 5-contact vertical Hall device. The model is based both on theoretical considerations and on FEM numerical simulations performed with COMSOL®. The result is a new predictive compact model, written in Verilog-A, with 7 input terminals and 14 parameters, mainly sensor geometrical and technological parameters. These parameters can be easily extracted from measurements carried out on a single sensor. The compact model has been validated by FEM simulations, as well as by comparing its response with experimental results obtained from a vertical Hall device fabricated in a CMOS 0.35 μm technology. The root mean square error of the model with respect to experimental results obtained on a wide range of typical sensor biasing conditions is below 2 %. Such a resistive model opens the way to an efficient, complete compact model of the vertical Hall device, i.e. including the Hall-effect as well as all the second-order galvanomagnetic effects.

2-D Differential Folded Vertical Hall Device Fabricated on a P-Type Substrate Using CMOS Technology

This paper investigates a two-dimensional (2-D) differential folded vertical Hall device (VHD) fabricated using standard 0.35 $\mu{\rm m}$ CMOS technology. To minimize the cross-coupling noise, the proposed VHD is laterally folded to shorten the effective conduction length, and a ${\rm p}^{+}$ guard ring shortens the effective conduction length to narrow the conducting channel. The proposed VHD is sensitive to in-plane magnetic induction based on the combinational magnetic effects between a bulk magnetotransistor (BMT), a vertical magnetoresistor (VMR), and a vertical magnetotransistor (VMT); and that the BMT is implemented with a p-substrate to enhance the magnetosensitivity. The measurement results show that the BMT is the dominant mechanism in view of a vertical magnetoresistor (VMR) and vertical magnetotransistor (VMT). Additionally, the VMT scales down the measurement range considerably whereas the VMR enhances the measurement range of the proposed VHD. The VMR is the key factor to increase the nonlinearity error. Integrating VMR with BMT or VMT enables high nonlinearity in a measured Hall voltage with respect to applied magnetic induction (B), but both the Hall voltage and the cross-coupling voltage are linear in B by integrating BMT with VMT. Additionally, the proposed VHD operates with small magnetic hysteresis, and its sensitivity is highest when bias current and bias voltage are low.

A Compact CMOS 3-D Magnetic Field Sensor

A ring-shape vertical hall device for X- and Y-direction, and a split-drain horizontal hall device for Z-direction are combined to implement the 3-D sensor. This merged design has the advantage of less area and lower power consumption. The sensitivities of vertical hall device (ring-shape magneto-resistor) and horizontal hall device (split-drain MAGFET) are estimated to be 0.11V/T and 2.88V/T respectively. Z-direction demonstrates a higher sensitivity. A high gain cascade differential amplifier is integrated with the sensor to further amplify the signal.

High-speed CMOS magnetic angle sensor based on miniaturized circular vertical Hall devices

We present a high-speed CMOS integrated magnetic angle sensor consisting of two 8-contact circular vertical Hall devices (CVHD). The biasing and sensing of the Hall voltage is rotated clockwise for the first device, and counter clockwise for the second one. The output voltages of the two devices are processed separately in two channels and they act as a reference signal one to another. The output of the sensor is a pulse width modulated signal whose width is proportional to twice the angle enclosed between the in-plane magnetic induction vector and the reference axis. The information on the angle is directly present in the pulse width modulated signal without the need for either arctg function implementation or complicated angle detection algorithms. The sensor's concept together with optimized interface and signal conditioning electronics allows for very high bandwidth. The measurement range of the sensor is 0–90°, with possibility for further extension. The sensor achieves tracking the angle of the in-plane magnetic vector oscillating at up to 200kHz (12,000,000rpm), or equivalently, having an angular speed of 628,000rad/s. To our knowledge, this is the highest bandwidth of a completely CMOS integrated magnetic angle sensor. The maximum absolute error for these speeds is ±4° without any calibration, the response time is 1μs, and the angular resolution is 0.5°.

A computationally efficient numerical model of the offset of CMOS-integrated vertical Hall devices

This paper describes a computationally efficient numerical model to study effects determining the offset of five-contact vertical Hall sensors (VHS). It applies a two-dimensional finite element model implemented in COMSOL Multiphysics and allows to take into account the junction field effect (JFE) altering the depletion layer width between n-well and p-doped regions as well as resistive asymmetries due to contact shifts. Doping profiles of realistic devices were extracted using SYNOPSYS TCAD simulations based on three sets of process parameters with different doping doses of the n-well and p+-diffusions. The VHS offset was compared with experimental results obtained using complementary metal oxide semiconductor (CMOS)-based VHS and analyzed as a function of the input voltage. It was shown that the linear offset components are modeled adequately by resistive imbalances caused by lateral contact shifts in the nanometer range. The JFE in turn is responsible for the nonlinear effects of dominantly quadratic dependence on the input voltage. Both effects contribute additively to the overall offset. According to the simulations, the nonlinear contribution is strongly reduced at higher n-well doping concentrations.

Analysis of the offset of semiconductor vertical Hall devices

This study investigates the origin of the offset voltage of five-contact vertical Hall sensors (5C-VHS) by modeling these devices as a simple lumped resistor circuit. The model with the shape of a four-contact Wheatstone bridge was enhanced by asymmetries caused by the mismatch of the lumped resistors. Further, the junction field effect was taken into account by modulating the resistances of the lumped elements with the average of the voltages applied at their contacts. The linear and quadratic components of the offset versus drive voltage characteristics in four operation modes were successfully traced back to the modeled asymmetries and nonlinearities. The measured offset characteristics of 5C-VHS is satisfactorily described and methods for reducing this undesired signal component are inferred.

Piezoresistive Response of Vertical Hall Devices

This paper reports on the piezoresistive response of CMOS-based five-contact vertical Hall sensors (VHS) under mechanical stress. Single sensor elements and coupled sensor systems comprising four individual VHS were exposed to normal in-plane stress σ <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">xx</sub> along the sensor axis using a four-point bending bridge setup. The resulting stress sensitivity of the offset signals at an input voltage of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> = 3 V was below 2 μV/MPa. In addition, an inhomogeneous stress distribution was generated by applying vertical forces close to the sensor systems using an SU-8 pillar. A resulting maximum offset increase by 109 μV/N at <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in</sub> = 3 V was measured. In conclusion, the influence of mechanical stress on the offset behavior of VHS is small compared to other offset sources such as the junction field effect and variations in sensor geometry.