Compact modeling of vertical hall-effect devices: electrical behavior

Abstract

This paper presents the development of a design-oriented compact model of vertical Hall-effect sensors integrated in CMOS technologies. Such a model makes easier the design of integrated Hall systems, permitting designers to co-simulate the Hall sensing element with the biasing and processing electronics thanks to a single electrical simulator. Here focus is put on the electrical behavior, i.e. the resistive behavior of a 5-contact vertical Hall device. The model is based both on theoretical considerations and on FEM numerical simulations performed with COMSOL®. The result is a new predictive compact model, written in Verilog-A, with 7 input terminals and 14 parameters, mainly sensor geometrical and technological parameters. These parameters can be easily extracted from measurements carried out on a single sensor. The compact model has been validated by FEM simulations, as well as by comparing its response with experimental results obtained from a vertical Hall device fabricated in a CMOS 0.35 μm technology. The root mean square error of the model with respect to experimental results obtained on a wide range of typical sensor biasing conditions is below 2 %. Such a resistive model opens the way to an efficient, complete compact model of the vertical Hall device, i.e. including the Hall-effect as well as all the second-order galvanomagnetic effects.