A Compact Behavioral Simulation Model for CMOS Vertical Hall-Effect Devices

Abstract

A compact behavioral simulation model for CMOS five-contact vertical Hall devices is presented. In term of the internal current flow geometry, the vertical Hall device is modeled based on an asymmetric Wheatstone bridge structure, including four current-controlled Hall voltage sources and four asymmetric lumped resistors. The lumped resistors on the Wheatstone bridge are calculated preliminarily by conformal mapping method. More importantly, the model takes into account the lateral diffusion effect and junction field effect which further improves the simulation accuracy. The behavioral model has been written in Verilog-A language with ten more physical and process parameters. The behavioral model simulation has been successfully performed in the Cadence Spectre environment with 0.8 μm high voltage CMOS technology parameters. The model’s simulation results are in good agreement with the reported experimental results.