A low-offset vertical Hall device with a couple of three-contact vertical Hall elements

Jun Xu Jun Xu,Yue Xu Yue Xu

doi:10.1109/icsict.2016.7999009

A low-offset vertical Hall device with a couple of three-contact vertical Hall elements

Jun Xu Jun Xu, Yue Xu Yue Xu

https://doi.org/10.1109/icsict.2016.7999009

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Publication Date: Oct 1, 2016

Citations: 2

Affiliation: Nanjing University of Posts and Telecommunications

#Vertical Hall Device #Μm High Voltage CMOS Technology + Show 8 more

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Abstract

Because of the electrical asymmetry, the traditional five-contact vertical Hall devices have large inherent offset. This paper presents a low-offset vertical Hall device with a couple of three-contact vertical Hall elements. Due to the good electrical symmetry of this new vertical Hall device, the inherent offset is significantly lower than that of a five-contact vertical Hall device. The simulation of this device was performed on Silvaco TCAD to analyze the performance of the vertical Hall device in a 0.8 µm high voltage CMOS technology. At 3V bias voltage, the simulated average offset voltage (Voff) at four spinning current modes is only 12.5 µV and the current related sensitivity (SI) is up to 180 V/AT.

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