A Vertical Hall Device in Standard Submicron CMOS Technology

Abstract

In order to lower the short circuit effect due to the measurement contacts, vertical Hall devices (VHD) are generally designed either in bulky N-type silicon or in the deep N-well of high-voltage CMOS technologies. In this last case, VHD can benefit from on chip circuitry for offset and 1/f noise reduction, but HVCMOS remains a costly technology. Recently, using spinning-current, a HVCMOS compatible VHD with a resolution of 76 muT over a 1.6 kHz bandwidth has been demonstrated. The VHD presented here is designed in the shallow N-well of a low cost 0.35 mum standard CMOS technology. Unlike conventional VHD, its measurement contacts are located outside the sensor active area. FEM simulations and experimental results show that the new geometry suppresses the short circuit effect and strongly reduces the intrinsic offset and noise. Thus, without any noise and offset reduction method, this new small VHD (63 mum2) reaches a resolution of 79 muT over a [5 Hz - 1.6 kHz] bandwidth.