2-D Differential Folded Vertical Hall Device Fabricated on a P-Type Substrate Using CMOS Technology

Abstract

This paper investigates a two-dimensional (2-D) differential folded vertical Hall device (VHD) fabricated using standard 0.35 $\mu{\rm m}$ CMOS technology. To minimize the cross-coupling noise, the proposed VHD is laterally folded to shorten the effective conduction length, and a ${\rm p}^{+}$ guard ring shortens the effective conduction length to narrow the conducting channel. The proposed VHD is sensitive to in-plane magnetic induction based on the combinational magnetic effects between a bulk magnetotransistor (BMT), a vertical magnetoresistor (VMR), and a vertical magnetotransistor (VMT); and that the BMT is implemented with a p-substrate to enhance the magnetosensitivity. The measurement results show that the BMT is the dominant mechanism in view of a vertical magnetoresistor (VMR) and vertical magnetotransistor (VMT). Additionally, the VMT scales down the measurement range considerably whereas the VMR enhances the measurement range of the proposed VHD. The VMR is the key factor to increase the nonlinearity error. Integrating VMR with BMT or VMT enables high nonlinearity in a measured Hall voltage with respect to applied magnetic induction (B), but both the Hall voltage and the cross-coupling voltage are linear in B by integrating BMT with VMT. Additionally, the proposed VHD operates with small magnetic hysteresis, and its sensitivity is highest when bias current and bias voltage are low.