Vertical Double-diffused Metal Oxide Research Articles

Novel SenseFET structure for VDMOS with adopting body reverse bias technique to adjust the reference current ratio

- Detecting current accurately and low-loss is an extremely important and challenging task in intelligent power switches. In the paper, the novel SenseFET structure, based on the Vertical Double-Diffused Metal Oxide Semiconductor (VDMOS) is proposed, which realizes variable reference current ratios by employing the body reverse bias technique. Several simulations are carried out, by using Sentaurus TCAD Software, to ensure that other performances of the sense transistor, with body reverse bias, are not affected. Compared to the constant reference current ratio, the new method improves the current sensing accuracy by 14% at 0.1 A, makes it easier to extract the targeted voltage by using a small reference current ratio at small load currents and reduces the power dissipation of the detection branch by using a large reference current ratio at large load currents. The structure, presented in this paper, provides the guiding methodology for a wide range of load current sensing and can be easily fabricated without adding additional mask.

Novel Vertical Power MOSFET With Step Hk Insulator Close to Super Junction Limit Relationship Between Breakdown Voltage and Specific ON-Resistance by Improving Electric Field Modulation

A new vertical double-diffused metal oxide semiconductor field effect transistor (MOSFET) is presented based on the high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> (Hk) MOSFET concept in this article with the step high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> insulator, named as step Hk vertical double-diffused metal oxide semiconductor (VDMOS), to improve the electric field modulation effect. For step Hk VDMOS, the depletion is increased by the electric field modulation effect of step Hk insulator, which decreases the specific on-resistance of step Hk VDMOS compared to the conventional Hk VDMOS. The various thickness of the Hk insulator modulates the vertical electric field distribution in the drift region, which increases the breakdown voltage (BV) of the step Hk VDMOS. Meanwhile, an analytical model for novel step Hk VDMOS is obtained by solving the 2-D Poisson equation in an N-type drift region, and the 2-D Laplace equation in the step Hk region, which can reasonably explain the modulation effect of the step Hk region on the electric field distribution. The results show that the BV of the step Hk VDMOS is increased from 639 V of the conventional Hk VDMOS to 736 V with the same drift length of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$42~\mu \text{m}$ </tex-math></inline-formula> . The theoretical results of the electrical characteristics are in good agreement with the results from numerical simulations.

Investigating the Failure Mechanism of Short-Circuit Tests in 1.2-kV SiC JBS-Integrated MOSFETs

In this article, the failure mechanism of a 1.2-kV monolithic junction barrier-controlled Schottky diode integrated silicon carbide metal–oxide–semiconductor field-effect transistor (JMOS) under short-circuit (SC) tests has been investigated by an experimental validation and simulation analysis. As a new type of device, JMOS has superior performance and chip area efficiency. However, the SC ruggedness of the JMOS needs further investigation. When comparing vertical double-diffused metal–oxide–semiconductor field-effect transistor (VDMOS) and JMOS devices in the SC test study, the leakage current of the JMOS is much higher than that of a common VDMOS. During the SC test, the JMOS drain current cannot be successfully suppressed after gate turn-off, and the thermionic emission current due to heat generation in the Schottky barrier diode (SBD) region continues flowing into the n-drift region. The SBD thermionic emission current is rapidly increased by the increasing lattice temperature, which can reach over 1600 K. Eventually, the JMOS undergoes thermal runaway due to positive electrothermal feedback. A mechanistic study was set up to analyze the relationship between the SC limit and the leakage current in the SBD region of the heated materials. Finally, the key to improve the SC ruggedness of the JMOS is decreasing the leakage current in the SBD region.

Breakdown Voltage Walk-in Phenomenon and Optimization for the Trench-Gate p-Type VDMOS Under Single Avalanche Stress

An anomalous breakdown voltage (BV) walk-in phenomenon of the trench-gate p-type vertical double-diffused metal–oxide–semiconductor (VDMOS) after single avalanche stress has been experimentally investigated. It is found that the BV of the VDMOS is decreased after the single avalanche stress, while other electrical parameters remain unchanged. T-CAD simulations and emission microscope (EMMI) analysis have been carried out. As a result, the shift of the breakdown point of the VDMOS, which results in the hot hole injection and trapping at the termination region, should be responsible for the BV degradation. A novel device structure with different trench depths in the termination region for the trench-gate p-type VDMOS is proposed to suppress the BV walk-in phenomenon.

Displacement damage on P-channel VDMOS caused by different energy protons

In this paper, characteristics of displacement and ionization damage on P-channel VDMOS (Vertical double-diffused Metal Oxide Semiconductor) deceives caused by 3 MeV and 6 MeV protons were investigated. The key electrical parameters such as threshold voltage and leakage current are measured. Experimental results show that threshold voltage move to left shift and the leakage current increases. The electrical properties measurement is performed in-situ by 3 MeV and 6 MeV protons, and the changes of electrical properties are different. The shift of threshold voltage is higher for the 6 MeV protons than for the 3 MeV ones. The leakage current is higher after the irradiation by 3 MeV protons than it by the 6 MeV ones. Annealing at room temperature for 300 days leads to an obvious decrease in the shift of threshold voltage, and has a little effect on leakage current. The increase in leakage current is mainly caused by displacement and the ionization damage mainly changes the shift of threshold voltage.

Model and Experiments of Small-Size Vertical Devices With Field Plate

A small-size vertical device with field plate is designed and experimentally realized in this paper. The modulation effect of the field plate causes an enhanced bulk electric field (ENBULF) and improves the breakdown voltage ${V}_{\textsf {B}}$ . A 2-D electric field model is developed to give the ENBULF condition corresponding to the maximum ${V}_{\textsf {B}}$ and the optimal specific ON-resistance ${R}_{ \mathrm{ON},\textsf {sp}}$ . Based on the model, the minimum figure of merit (FOM) (gate charge ${Q}_{\textsf {g}}\times \mathrm{\scriptstyle ON}$ -resistance ${R}_{ \mathrm{ON}}$ ) is discussed for a typical ENBULF device, i.e., the shield-gate vertical double diffused metal–oxide–semiconductor (SG-VDMOS). The calculated results are in good agreement with the simulations. Furthermore, a 35-V SG-VDMOS is analytically designed and experimentally implemented, which obtains a ${R}_{ \mathrm{ON},\textsf {sp}}$ of 4.4 $\text{m}\Omega \cdot \textsf {mm}^{2}$ and a gate to drain charge ${Q}_{\textsf {gd}}$ of 11.3 nC, respectively. The experiment realizes the minimal FOM and a ${R}_{ \mathrm{ON},\textsf {sp}}$ reduced by 28.6% when compared with the conventional “silicon limit.”

Incorporation of hafnium and platinum metal in vertical power MOSFETs

A novel, vertical single-diffused metal–oxide–semiconductor (VSDMOS) structure is proposed by applying workfunction engineering to a vertical power metal–oxide–semiconductor field-effect transistor (MOSFET) with source and drain regions formed using the charge plasma concept. Electron and hole plasma was induced by employing hafnium and platinum metal. Furthermore, the electrical characteristics of the proposed VSDMOS were compared with those of conventional vertical double-diffused metal–oxide–semiconductor devices, revealing that the proposed VSDMOS exhibits a 14 % increase in current driving capability, with improved breakdown voltage.

High electric field stress model of n-channel VDMOSFET based on artificial neural network

In VDMOSFETs (Vertical Double-Diffused Metal-Oxide Semiconductor Field-Effect Transistor), in the cases when the voltage at the gate contact comes close to the breakdown voltage, a high electric field (HEF) is formed in the gate oxide. This leads to the generation of fixed and mobile charged defects in the gate oxide and at the silicon/oxide interface. The mechanisms of defects formation are very complex, so it is impossible to create a unique physical model that could describe the behavior of components, i.e., its electrical characteristics, depending on the stress voltage and the stress time. In cases like this, the application of artificial neural network (ANN) has proved to be one of the acceptable solution. In fact, this approach can give the very accurate models for the define range of changes of the input parameters, without going into very complex physical and chemical processes that occur in the structure of the components. All that is necessary to generate the ANN model is the sufficiently large number of the measured data and correct selection of the neural network structure and appropriate training algorithm. In this paper, we have applied the multilayer feedforward neural networks to the model of high electric field stress effects (HEFS) in the n-channel VDMOS power transistor. Experimentally measured transfer characteristics for different times of stress were used to train the neural networks of different configurations. In addition, the influence of several different training algorithms on the accuracy of the model was studied. It is shown that a properly selected neural network structure and training algorithm provide the ANN model of HEFS of the n-channel VDMOS power transistor that very precisely gives its electrical characteristics (transfer characteristic and threshold voltage) for a given stress voltage and temperature in the whole range of the time stress changes from 0 to 150 min.

Effects of consecutive irradiation and bias temperature stress in p-channel power vertical double-diffused metal oxide semiconductor transistors

The mechanisms responsible for the effects of consecutive irradiation and negative bias temperature (NBT) stress in p-channel power vertical double-diffused MOS (VDMOS) transistors are presented in this paper. The investigation was performed in order to clarify the mechanisms responsible for the effects of specific kind of stress in devices previously subjected to the other kind of stress. In addition, it may help in assessing the behaviour of devices subjected to simultaneous irradiation and NBT stressing. It is shown that irradiation of previously NBT stressed devices leads to additional build-up of oxide trapped charge and interface traps, while NBT stress effects in previously irradiated devices depend on gate bias applied during irradiation and on the total dose received. In the cases of low-dose irradiation or irradiation without gate bias, the subsequent NBT stress leads to slight further device degradation. On the other hand, in the cases of devices previously irradiated to high doses or with gate bias applied during irradiation, NBT stress may have a positive role, as it actually anneals a part of radiation-induced degradation.

Dislocation-Induced Punchthrough Causing Drain-to-Source Leakage Current in Power VD MOSFET Structures

A detailed characterization of the leakage in semiconductor devices is essential for proper adjustment of the manufacturing process in order to eliminate the leakage. Subsurface punchthrough was determined as the leakage current mechanism in the power vertical double-diffused metal–oxide–semiconductor field-effect-transistor, and the quadratic dependence of the drain current was confirmed for the leakage caused by the punchthrough. A failure analysis revealed a large number of dislocations located in the corners of transistor cells. The majority of the detected dislocations were electrically inactive. Dislocation depth measurement indicated that only a small number of the dislocations penetrated deep into the channel, i.e., penetrated from source area to the boron-doped p− transistor channel. The transistor channel shortening caused by the enhanced phosphorus diffusion along the dislocations was determined as the root cause of the leakage. The diffusion spikes of the phosphorus atoms lengthened the n+ source layer, and the interface of the n+ and p− layer was shifted into the transistor channel at the site of the dislocation. Manufacturing process experiments related to the channel lengthening and the channel doping confirmed the theory of the dislocation-induced channel shortening. The occurrence of dislocations was attributed to the surface stress induced by the improper conditions of oxide growing and plasma etching in the affected regions.

NBTI and Irradiation Effects in P-Channel Power VDMOS Transistors

In this paper, we report the results of consecutive irradiation and negative bias temperature (NBT) stress experiments performed on p-channel power vertical double-diffused metal–oxide semiconductor transistors. The purpose is to examine the effects of a specific kind of stress in devices previously subjected to the other kind of stress, as well as to assess if possible the behavior of devices subjected to simultaneous irradiation and NBT stressing. It is shown that irradiation of previously NBT stressed devices leads to a further increase of negative threshold voltage shift due to additional build-up of both oxide trapped charge and interface traps. NBT stress effects in previously irradiated devices may, however, depend on gate bias applied during irradiation and on the total dose received: in the cases of low-dose irradiation or irradiation without gate bias, the subsequent NBT stress seems to lead to further device degradation, whereas in the cases of devices previously irradiated to high doses or with gate bias applied during irradiation, NBT stress seems to have a positive role since it practically anneals a part of radiation-induced degradation.

Analysis of recoverable and permanent components of threshold voltage shift in NBT stressed p-channel power VDMOSFET**Project supported by the Fund from the Ministry of Education, Science and Technological Development of the Republic of Serbia (Grant Nos. OI-171026 and TR-32026) and the Ei PCB Factory, Niš.

In this study we investigate the dynamic recovery effects in IRF9520 commercial p-channel power vertical double diffused metal–oxide semiconductor field-effect transistors (VDMOSFETs) subjected to negative bias temperature (NBT) stressing under the particular pulsed bias. Particular values of the pulsed stress voltage frequency and duty cycle are chosen in order to analyze the recoverable and permanent components of stress-induced threshold voltage shift in detail. The results are discussed in terms of the mechanisms responsible for buildup of oxide charge and interface traps. The partial recovery during the low level of pulsed gate voltage is ascribed to the removal of recoverable component of degradation, i.e., to passivation/neutralization of shallow oxide traps that are not transformed into the deeper traps (permanent component). Considering the value of characteristic time constant associated with complete removal of the recoverable component of degradation, it is shown that by selecting an appropriate combination of the frequency and duty cycle, the threshold voltage shifts induced under the pulsed negative bias temperature stress conditions can be significantly reduced, which may be utilized for improving the device lifetime in real application circuits.

Annealing influence on recovery of electrically stressed power vertical double-diffused metal oxide semiconductor transistors

The effect of annealing on the recovery of electrically stressed power vertical double-diffused metal oxide semiconductor (VDMOS) transistors has been investigated. Behaviors of device threshold voltage and channel carrier mobility have been analyzed in terms of underlying changes in the densities of gate oxide charges and interface traps. The mechanisms responsible for the above-mentioned changes during the recovery of stressed devices have been analyzed as well. The annealing resulted in achieving stable threshold voltage and mobility, but did not ensure full recovery, as part of the stress-induced degradation remained permanent and could not be annealed. Namely, the annealing was found to enhance the neutralization of stress-induced oxide charges and the passivation of stress-induced interface traps, while the stability upon its completion resulted from the significantly decreased density of gate oxide charges and the possible balance between the processes of trap passivation and creation at the SiO2–Si interface.

Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices.

Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines.

Ultra-low specific on-resistance vertical double-diffused metal—oxide semiconductor with a high-k dielectric-filled extended trench

An ultra-low specific on-resistance trench gate vertical double-diffused metal-oxide semiconductor with a high-k dielectric-filled extended trench (HK TG VDMOS) is proposed in this paper. The HK TG VDMOS features a high-k (HK) trench below the trench gate. Firstly, the extended HK trench not only causes an assistant depletion of the n-drift region, but also optimizes the electric field, which therefore reduces Ron,sp and increases the breakdown voltage (BV). Secondly, the extended HK trench weakens the sensitivity of BV to the n-drift doping concentration. Thirdly, compared with the superjunction (SJ) vertical double-diffused metal-oxide semiconductor (VDMOS), the new device is simplified in fabrication by etching and filling the extended trench. The HK TG VDMOS with BV = 172 V and Ron,sp = 0.85 mΩ·cm2 is obtained by simulation; its Ron,sp is reduced by 67% and 40% and its BV is increased by about 15% and 5%, in comparison with those of the conventional trench gate VDMOS (TG VDMOS) and conventional superjunction trench gate VDMOS(SJ TG CDMOS).

Novel Design of Vertical Double-Diffused Metal–Oxide–Semiconductor Transistor for High Electrostatic Discharge Robustness

[Bipolar]-[complementary metal–oxide–semiconductor transistor (CMOS)]–[double-diffused metal–oxide–semiconductor transistor (DMOS)] [BiC–DMOS] devices are widely used in high-voltage applications. As some applications require high electrostatic discharge (ESD) robustness, we studied the vertical DMOS (VDMOS) transistor to improve ESD robustness. In this paper, we propose a balanced VDMOS (B-VDMOS) transistor. A B-VDMOS transistor is optimized for a cell layout to improve current uniformity after avalanche breakdown by arranging a number of sources. As the B-VDMOS transistor can prevent current concentration, it is not destroyed after avalanche breakdown and acquires a high second breakdown current. Owing to the high second breakdown current, the B-VDMOS transistor can improve ESD robustness by 50% according to the human body model (HBM) test compared with a conventional VDMOS (C-VDMOS) transistor. As the B-VDMOS transistor has high ESD robustness, it can be used in harsh applications and systems.

Turn-Around of Threshold Voltage in Gate Bias Stressed p-Channel Power Vertical Double-Diffused Metal–Oxide–Semiconductor Transistors

The “turn-around” of threshold voltage in high gate electric field stressed p-channel power vertical double-diffused metal–oxide–semiconductor (VDMOS) transistors was observed and analyzed in details. This unexpected effect was observed only in devices stressed by enough high positive gate voltages, leading to the gate electric fields above 6.3 MV/cm, and it was more pronounced in those stressed by higher voltages, when threshold voltage shift exhibited very strong dependence on stressing time. The quantitative analysis of the results obtained revealed that stress-induced instabilities of the gate oxide charge and interface traps, due to a complex electrochemical processes occurring in the gate oxide and at silicon–oxide interface during the stressing, were responsible for the observed “turn-around” effect.

VDMOSFET model parameter extraction based on electrical and optical measurements

Lateral device parameters for VDMOSFET (Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistor) with hexagonal cells are extracted using an original method based on electrical and optical measurements. Using microscopic observation of the ship of the device and C–V characterization, the lateral device structure parameters could be extracted. Values of the extracted parameters are in good agreement with the values given by the manufacturer. The advantage of this method is the high precision of results for a low cost. Perhaps the most important point of this method is that it can replace the other techniques usually employed, wherein devices are destroyed to obtain the cross section of the structure. The proposed technique can be very useful for analyzing any complex geometrical structure of VDMOS transistors (hexagonal, triangular, square etc…).

VDMOSFET Model Parameter Extraction Based on Electrical and Optical Measurements

Lateral Device parameters for VDMOSFET (Vertical double diffused metal oxide semiconductor field effect transistor) with hexagonal cells has been extracted by an original model based on electrical and optical measurements. Using microscopic observation for the ship of the device and by C-V characterization, the lateral device structure parameters could be extracted. Values of the extracted parameters are in good correlation with the values given by the manufactured. Advantage of this model the high precision results with a low cost. Perhaps, the most important point in this model, that we can replace the other techniques usually employed in this study where we destroyed the device for cut and cross section of the structure. The proposed technique in this paper can be very useful for analyzing any complex geometrical structure of VDMOS transistors (hexagonal, triangular, square <em>etc</em>...).

Molybdenum Film Technology For Power Metal Oxide Semiconductor Field Effect Transistor Gate Electrode Applications

Molybdenum (Mo) film as a gate electrode for high-frequency power metal oxide semiconductor field effect transistor (MOSFET) has been investigated. The Mo films were deposited by sputtering in Ar ambient. The Mo films properties depend greatly on the substrate temperature. An accurate pattern was realized for Mo film. Stability and reliability of Mo gates for high-frequency power vertical double-diffused metal oxide semiconductor field effect transistors (VDMOSFETs) are as good as those of polysilicon gates. The shift of threshold voltage is below ±35 mV and the change of gate-source leakage current is less than 5 nA under the stress condition of ±5 MV/cm for 100 h at 250°C. Power gain and drain efficiency improvement of Mo gates for VDMOSFETs have been obtained.