Utilization Of Field Programmable Gate Arrays Research Articles

FPGA acceleration of convolutional neural networks: Current applications and future prospects

In the contemporary era of big data, the utilization of deep learning technology has become widespread in the extraction of valuable analytical insights from the data under consideration. This technology finds extensive applications in various domains, including image information recognition, speech processing, and text language analysis. When it comes to accelerating convolutional neural networks (CNNs), the utilization of Field-Programmable Gate Arrays (FPGAs) offers distinct advantages over other hardware accelerators. Nevertheless, it is important to acknowledge that FPGA-based acceleration also comes with its own structural limitations. This article places its focus on two main aspects: firstly, it delves into the present-day application landscape and the latest developmental trajectories of convolutional neural networks. Secondly, it elucidates the inherent characteristics of FPGA implementations of CNNs. Furthermore, the article conducts a comprehensive examination of the pertinent constraints associated with FPGA-accelerated deep learning algorithms. The discussion extends beyond the present moment and ventures into the future, offering insights into the potential advancements in the field of deep learning. Importantly, it also brings into focus the prospective avenues for further research regarding the application of FPGAs in the domain of convolutional neural networks.

Deploying Multi-tenant FPGAs within Linux-based Cloud Infrastructure

Cloud deployments now increasingly exploit Field-Programmable Gate Array (FPGA) accelerators as part of virtual instances. While cloud FPGAs are still essentially single-tenant, the growing demand for efficient hardware acceleration paves the way to FPGA multi-tenancy. It then becomes necessary to explore architectures, design flows, and resource management features that aim at exposing multi-tenant FPGAs to the cloud users. In this article, we discuss a hardware/software architecture that supports provisioning space-shared FPGAs in Kernel-based Virtual Machine (KVM) clouds. The proposed hardware/software architecture introduces an FPGA organization that improves hardware consolidation and support hardware elasticity with minimal data movement overhead. It also relies on VirtIO to decrease communication latency between hardware and software domains. Prototyping the proposed architecture with a Virtex UltraScale+ FPGA demonstrated near specification maximum frequency for on-chip data movement and high throughput in virtual instance access to hardware accelerators. We demonstrate similar performance compared to single-tenant deployment while increasing FPGA utilization, which is one of the goals of virtualization. Overall, our FPGA design achieved about 2× higher maximum frequency than the state of the art and a bandwidth reaching up to 28 Gbps on 32-bit data width.

A Sub-μ W Reversed-Body-Bias 8-bit Processor on 65-nm Silicon-on-Thin-Box (SOTB) for IoT Applications

For most Internet-of-Things (IoT) applications, embedded processors typically execute lightweight tasks such as sensing and communication. The typical IoT program senses some information and sends them via a channel, usually a wireless channel with an RF circuit. These IoT nodes often require a system with networking capabilities and a low-power harvester implementation. This brief presents a sub- μW 8-bit processor which is suitable for such IoT applications. The processor implements the Open8 Instruction Set Architecture (ISA) with an 8-bit datapath and 16-bit bus addressing. The chip contains the processor and a 4-KB of Static Random-Access-Memory (SRAM), and is fabricated by the 65-nm Silicon-On-Thin-Box (SOTB) process. The SOTB process is one of the Fully-Depleted Silicon-On-Insulator (FD-SOI) technology. Hence, the ability to control biasing voltages is one of its key advantages to achieve low-power. The experimental results show that the power consumption at the reverse-body bias can reach down to 50-nW with 0.5-V supply voltage and 32-KHz operating clock frequency. The completed microcontroller consists of the Open8 processor, 32-KB of Read-Only-Memory (ROM), 4-KB of SRAM, Serial Peripheral Interface (SPI), SPI programmer, debug module, General-Purpose In-Outs (GPIOs), and UART. The system was tested using an XC7A100T Xilinx Field-Programmable Gate Array (FPGA); it yielded 1.8% of the total FPGA utilization.

Implementation of FPGA accelerator architecture for Convolution Neural Network in Emotional Recognition System

The field of deep learning, artificial intelligence has arisen due to the later advancements in computerized innovation and the accessibility of data information, has exhibited its ability and adequacy in taking care of complex issues in learning that were not previously conceivable. The viability in emotional detection and acknowledging specific applications have demonstrated by Convolution neural networks (CNNs). In any case, concentrated Processor activities and memory transfer speed are necessitated that cause general CPUs to neglect to accomplish the ideal degrees of execution. Subsequently, to build the throughput of CNNs, equipment quickening agents utilizing General Processing Units (GPUs), Field Programmable Gate Array (FPGAs) and Application Specific Integrated circuits (ASICs) has been used. We feature the primary highlights utilized for productivity improving by various techniques for speeding up. Likewise, we offer rules to upgrade the utilization of FPGAs for the speeding up of CNNs. The proposed algorithm on to an FPGA platform and show that emotions recognition utterance duration 1.5s is identified in 1.75ms, while utilizing 75% of the resources. This further demonstrates the suitability of our approach for real-time applications on Emotional Recognition system.

Array Multiplier and CIA based FIR Filter for DSP applications

In Field Programmable Gate Array (FPGA) platform, Finite Impulse Response (FIR) filter is one of the important applications in the context of Digital Signal Processing (DSP). The traditional FIR is designed using a number of the adders, multipliers which enlarge the area of the filter architecture. Generally, the multiplier and adder are required to design the FIR filter. In this research, Array Multiplier (AM) is used in the Processing Element (PE) for multiply the filter inputs with coefficients. This research employs the Carry Increment Adder (CIA) in the accumulator for the adding output of the PE. The proposed method is named as AM -CIA-FIR filter. Due to the usage of AM and CIA adder, the hardware utilization of the proposed work is improved. The AM -CIA-FIR filter is implemented in Xilinx ISE software by using Verilog code on different Virtex devices in terms of Virtex-4, Virtex-5, and Virtex-6. This experiment results showed that AM -CIA-FIR filter has reduced 14.01 % of the FPGA utilization compared to the PSA-FIR filter design.

MapReduce Model Using FPGA Acceleration for Chromosome Y Sequence Mapping

Genome assemblies sequenced by a Whole Genome Shotgun (WGS) project predict an organism's function and history. Sequence alignment is the foundation of bioinformatics by a computational search through large genome sequence databases, which generally requires enormous amounts of memory and takes a long execution time. In this paper, an Optimized Smith-Waterman algorithm based on the Gotoh algorithm with an affine gap for accuracy alignment, the divide and conquer technique, and the MapReduce framework implemented to establish a parallel process. This model was implemented on Virtex 7 field-programmable gate arrays (FPGAs). These techniques provide a better performance, reduce the hardware requirements, improve the accuracy, increase the computational throughput, and accelerate the alignment process for big data available in a complete Y chromosome. The hardware proposed system can achieve high performance, low time consumption 1.699 ns, and decrease FPGA utilization for big data alignments Y chromosome is used as an example.

Utilization of FPGA for Onboard Inference of Landmark Localization in CNN-Based Spacecraft Pose Estimation

In the recent past, research on the utilization of deep learning algorithms for space applications has been widespread. One of the areas where such algorithms are gaining attention is in spacecraft pose estimation, which is a fundamental requirement in many spacecraft rendezvous and navigation operations. Nevertheless, the application of such algorithms in space operations faces unique challenges compared to application in terrestrial operations. In the latter, they are facilitated by powerful computers, servers, and shared resources, such as cloud services. However, these resources are limited in space environment and spacecrafts. Hence, to take advantage of these algorithms, an on-board inferencing that is power- and cost-effective is required. This paper investigates the use of a hybrid Field Programmable Gate Array (FPGA) and Systems-on-Chip (SoC) device for efficient onboard inferencing of the Convolutional Neural Network (CNN) part of such pose estimation methods. In this study, Xilinx’s Zynq UltraScale+ MPSoC device is used and proposed as an effective onboard-inferencing solution. The performance of the onboard and computer inferencing is compared, and the effectiveness of the hybrid FPGA-CPU architecture is verified. The FPGA-based inference has comparable accuracy to the PC-based inference with an average RMS error difference of less than 0.55. Two CNN models that are based on encoder-decoder architecture have been investigated in this study and three approaches demonstrated for landmarks localization.

The Costs of Confidentiality in Virtualized FPGAs

Some modern datacenters are augmenting their compute infrastructure by deploying field-programmable gate arrays (FPGAs) to provide users with specialized accelerators that offer superior compute capability, increased energy efficiency, lower latency, and more programming flexibility than CPUs. However, the higher programming flexibility of FPGAs also gives more capabilities to malicious users to remotely sniff data from other applications running on the same FPGA. This has created a challenge for efficient utilization of FPGAs in datacenters: FPGAs in datacenters are currently not shared between users due to potential security risks. In this paper, we propose different techniques to defeat data-sniffing attacks in datacenter FPGAs by encrypting/decrypting the user application’s data. We describe techniques that are appropriate to different trust levels and rigorously evaluate the costs of these data confidentiality techniques in current virtualized FPGAs. In addition, for each trust level, we propose an architectural change to the FPGA to mitigate the costs of providing data confidentiality. We also investigate the role of interconnect in these architectural changes and demonstrate that more efficient security features can be implemented together with the interconnect if the FPGAs use a hard network on chip.

D-TCAM: A High-Performance Distributed RAM Based TCAM Architecture on FPGAs

Ternary content-addressable memory (TCAM) is a high-speed searching device that searches the entire memory in parallel in deterministic time, unlike random-access memory (RAM), which searches sequentially. A network router classifies and forwards a data packet with the aid of a TCAM that stores the routing data in a table. Field-programmable gate arrays (FPGAs), due to its hardware-like performance and software-like reconfigurability, are widely used in networking systems where TCAM is an essential component. TCAM is not included in modern FPGAs, which leads to the emulation of TCAM using available resources on FPGA. Several emulated TCAM designs are presented but they lack the efficient utilization of FPGA's hardware resources. In this paper, we present a novel TCAM architecture, the distributed RAM based TCAM (D-TCAM), using D-CAM as a building block. One D-CAM block implements a 48-bytes TCAM using 64 lookup tables (LUTs), that is cascaded horizontally and vertically to increase the width and depth of TCAM, respectively. A sample size of 512 x 144 is implemented on Xilinx Virtex-6 FPGA, which reduced the hardware utilization by 60% compared to the state-of-the-art FPGA-based TCAMs. Similarly, by exploiting the LUT-flip-flip (LUT-FF) pair nature of Xilinx FPGAs, the proposed TCAM architecture improves throughput by 58.8% without any additional hardware cost.

FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review

Due to recent advances in digital technologies, and availability of credible data, an area of artificial intelligence, deep learning, has emerged, and has demonstrated its ability and effectiveness in solving complex learning problems not possible before. In particular, convolution neural networks (CNNs) have demonstrated their effectiveness in image detection and recognition applications. However, they require intensive CPU operations and memory bandwidth that make general CPUs fail to achieve desired performance levels. Consequently, hardware accelerators that use application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), and graphic processing units (GPUs) have been employed to improve the throughput of CNNs. More precisely, FPGAs have been recently adopted for accelerating the implementation of deep learning networks due to their ability to maximize parallelism as well as due to their energy efficiency. In this paper, we review recent existing techniques for accelerating deep learning networks on FPGAs. We highlight the key features employed by the various techniques for improving the acceleration performance. In addition, we provide recommendations for enhancing the utilization of FPGAs for CNNs acceleration. The techniques investigated in this paper represent the recent trends in FPGA-based accelerators of deep learning networks. Thus, this review is expected to direct the future advances on efficient hardware accelerators and to be useful for deep learning researchers.

Parallel-Pipelined-Memory-Based Blowfish Design with Reduced FPGA Utilization for Secure ZigBee Real-Time Transmission

Data security is currently become a serious concern in wireless communication system for both the users and providers. Without a secure medium, the data transmission is exposed to various types of wireless attacks. Therefore, this paper focuses on the development of a high performance parallel-pipelined-memory-based (P2M) Blowfish as a security design with reduced field programmable gate array (FPGA) utilization, which is the best security design to be embedded in the mobile devices. Through FPGA platform, the performance of the proposed Blowfish shows that a throughput increases by 10.5%, with the hardware utilization and power consumption decrease by 3.5% and 21%, respectively. The P2M Blowfish was validated in two-way communication channel by using FPGA-based radio platform together with ZigBee technology and the real-time transmission was measured in terms of bit-error-rate, received power and communication range. These characteristics have proven that the proposed P2M Blowfish possesses the ability to replace the advanced encryption standard which is known as a complex algorithm employed by most of the wireless communication standards.

Towards Efficient Task Scheduling on 2D Reconfigurable FPGAs

With the rapid development of dynamical partial reconfiguration technology, FPGA (Field Programmable Gate Array) is able to allow independent tasks to be executed concurrently without interfering with each other, which increases its flexibility and performance, but on the other hand leads to multi-task scheduling problem. The task scheduling in this paper is the problem of task sequencing, which adjusts the entering sequence of the incoming tasks with the consideration of the attributes of tasks and the utilization of FPGA. A conditional preemption based task sequencing method is proposed that allows tasks that arrive later to be executed in advance as long as the previous tasks can still be guaranteed to enter the FPGA on time. Simulations show that these methods can effectively decrease the waiting ratio of task sets, thus improving the flexibility and utilization of FPGA.

Clustering scheduling for hardware tasks in reconfigurable computing systems

Reconfigurable computing systems have been used widely in various areas due to their attractive features in low-power and high-precision. However, how to increase utilization and throughput while reducing configuration and execution time overheads on large-scale data has become a great challenge for reconfigurable computing systems. In this paper, we employ a directed acyclic graph (DAG) to represent the tasks in an application. With considerations of task dependencies and resource constraints that are not sufficiently studied in literature, we propose two clustering scheduling strategies to reduce the number of configurations and the execution time of applications, while enhancing the utilization of field programmable gate array (FPGA) devices: One is a heuristic scheduling strategy and the other is a dynamic programming scheduling strategy. Experimental results indicate that our dynamic programming scheduling strategy can significantly reduce the number of configurations and improve the FPGA utilization, compared to the heuristic scheduling strategy.

Analysis of Scheduling the Independent CCHBs for Partially Reconfigurable FPGA

The emerging reconfigurable computing reduces the need of computation exhaustive applications, which are always demanding more efficient computation hardware. The partially reconfigurable Field Programmable Gate Arrays (FPGA) are highly suitable for performance improvement. This paper discusses the study of FPGA utilization when scheduling fixed size configurable computation hardware block (CCHB) by applying a heuristic. Based on the parameters (speedup, CCHB size etc.,) associated with the independent CCHBs, scheduling is performed and it is repeated for various sizes of FPGA. From the study of four applications from benchmark suite, it is observed that the device utilization is increased with size of CCHBs not greater than 0.5 times or not less than 0.85 times of the size of FPGA.

Analysis of Scheduling the Independent CCHBs for Partially Reconfigurable FPGA

The emerging reconfigurable computing reduces the need of computation exhaustive applications, which are always demanding more efficient computation hardware. The partially reconfigurable Field Programmable Gate Arrays (FPGA) are highly suitable for performance improvement. This paper discusses the study of FPGA utilization when scheduling fixed size configurable computation hardware block (CCHB) by applying a heuristic. Based on the parameters (speedup, CCHB size etc.,) associated with the independent CCHBs, scheduling is performed and it is repeated for various sizes of FPGA. From the study of four applications from benchmark suite, it is observed that the device utilization is increased with size of CCHBs not greater than 0.5 times or not less than 0.85 times of the size of FPGA.

Floorplanning for High Utilization of Heterogeneous FPGAs

Heterogeneous resources such as configurable logic blocks (CLBs), multiplier blocks (MULs) and ram blocks (RAMs) where millions of logic gates (a growing trend to implement larger and more complex functions) included have been added to field programmable gate arrays (FPGAs). And floorplanning for this, hierarchical approach is recognized as the most effective method. The FPGA architecture shows that CLBs hold the maximum quantity much more than other resources. Therefore, making a high utilization of them means an enhancement of the FPGA densities. This paper presents a three-phase floorplanning method for heterogeneous FPGAs. The proposed method can make the resource requirement of functional modules satisfied with a high resource utilization. First, we use a non-slicing floorplanning method to optimize the wirelength, however, in this phase, the satisfaction of resource requirements from functional modules might fail. Second, a min-cost-max-flow algorithm is used to tune the assignment of CLBs to functional modules, such that all the functional modules get CLB requirements satisfied. Finally, the MULs and RAMs are allocated to modules by a network flow model. The results show that about 7%-85% wirelength reduction is obtained, and CLB utilization is improved by about 25%.

Design and Implementation of a Sort-Free K-Best Sphere Decoder

This paper describes the design and very-large-scale integration (VLSI) architecture for a 4 × 4 breadth-first K-best multiple-input-multiple-output (MIMO) decoder using a 64 quadrature-amplitude modulation (QAM) scheme. A novel sort-free approach to path extension, as well as quantized metrics result in a high-throughput VLSI architecture with lower power and area consumption compared to state-of-the-art published systems. Functionality is confirmed via a field-programmable gate array (FPGA) implementation on a Xilinx Virtex II Pro FPGA. Comparison of simulation and measurements are given, and FPGA utilization figures are provided. Finally, VLSI architectural tradeoffs are explored for a synthesized application-specific IC (ASIC) implementation in a 65-nm CMOS technology.

Increasing Design Changeability Using Dynamic Partial Reconfiguration

In order to be able to change the functionality of filters and other data acquisition algorithms after their installation, it has been common for years to utilize reconfigurable field-programmable gate arrays (FPGAs) for data filtering and data forwarding. This paper presents a framework built to take advantage of an enhanced reconfiguration technology called dynamic partial reconfiguration (DPR). It is shown how this framework is designed and how it can be used to get a quick and easy access to DPR. Current case study measurements are presented and a short outlook illustrates how DPR could help to significantly increase the changeability of FPGAs regarding typical data acquisition applications and algorithms, which could finally lead to a better capacity utilization of FPGAs.

ATOMi: an algorithm for circuit partitioning into multiple FPGAs using time-multiplexed, off-chip, multicasting interconnection architecture

Logic emulation is so far the fastest method to verify the system functionality in the gate level before chip fabrication. Field-programmable gate array (FPGA)-based logic emulator with large gate capacity generally comprises a large number of FPGAs or special processors connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. This paper first describes a new interconnection architecture called TOMi (Time-multiplexed, Off-chip, Multicasting interconnection) and proposes a circuit partitioning algorithm called ATOMi (Algorithm for TOMi) for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi. ATOMi reduces the number of off-chip signal transfers to optimize the performance for multi-FPGA system implemented by TOMi. Experimental results using Partitioning93 benchmarks show that, by adopting the proposed TOMi interconnection architecture along with ATOMi, the pin count is reduced to 14.4%-88.6% while the critical path delay is reduced to 66.1%-90.1% compared to traditional architectures including mesh, crossbar, and VirtualWire architecture.

Testing and diagnosis of interconnect faults in cluster-based FPGA architectures

As IC densities are increasing, cluster-based field programmable gate arrays (FPGA) architectures are becoming the architecture of choice for major FPGA manufacturers. A cluster-base architecture is one in which several logic blocks are grouped together into a coarse-grained logic block. While the high-density local interconnect often found within clusters serves to improve FPGA utilization, it also greatly complicates the FPGA interconnect testing problem. To address this issue, we have developed a hierarchical approach to define a set of FPGA configurations which enable interconnect fault detection and diagnosis. This technique enables the detection of bridging faults involving intracluster interconnect and extracluster interconnect. The hierarchical structure of a cluster-based tile is exploited to define intracluster configurations separately from extracluster configurations, thereby improving the efficiency of the configuration definition process. The cornerstone of this work is the concise expression of the detectability conditions of each fault and the distinguishability conditions of each fault pair. By guaranteeing that both intracluster and extracluster configurations have several test transparency properties, hierarchical fault detectability is ensured.