Analysis of Scheduling the Independent CCHBs for Partially Reconfigurable FPGA

Abstract

The emerging reconfigurable computing reduces the need of computation exhaustive applications, which are always demanding more efficient computation hardware. The partially reconfigurable Field Programmable Gate Arrays (FPGA) are highly suitable for performance improvement. This paper discusses the study of FPGA utilization when scheduling fixed size configurable computation hardware block (CCHB) by applying a heuristic. Based on the parameters (speedup, CCHB size etc.,) associated with the independent CCHBs, scheduling is performed and it is repeated for various sizes of FPGA. From the study of four applications from benchmark suite, it is observed that the device utilization is increased with size of CCHBs not greater than 0.5 times or not less than 0.85 times of the size of FPGA.