Implementation of FPGA accelerator architecture for Convolution Neural Network in Emotional Recognition System

Samson Immanuel J Et.Al

doi:10.17762/turcomat.v12i6.1277

Abstract

The field of deep learning, artificial intelligence has arisen due to the later advancements in computerized innovation and the accessibility of data information, has exhibited its ability and adequacy in taking care of complex issues in learning that were not previously conceivable. The viability in emotional detection and acknowledging specific applications have demonstrated by Convolution neural networks (CNNs). In any case, concentrated Processor activities and memory transfer speed are necessitated that cause general CPUs to neglect to accomplish the ideal degrees of execution. Subsequently, to build the throughput of CNNs, equipment quickening agents utilizing General Processing Units (GPUs), Field Programmable Gate Array (FPGAs) and Application Specific Integrated circuits (ASICs) has been used. We feature the primary highlights utilized for productivity improving by various techniques for speeding up. Likewise, we offer rules to upgrade the utilization of FPGAs for the speeding up of CNNs. The proposed algorithm on to an FPGA platform and show that emotions recognition utterance duration 1.5s is identified in 1.75ms, while utilizing 75% of the resources. This further demonstrates the suitability of our approach for real-time applications on Emotional Recognition system.

Highlights

On account of the arrangement of enormous measures of valid information (Big Data: Audio, Video, Text, and so forth), and colossal advances inside the space of computerized material science innovations that offer huge processing power, there has been a recovery inside the space of figuring Artificial Intelligence (AI), strikingly inside the space of Deep learning (DL)
CNN computations are performing through unique style of cycle element modules in FPGA. the most modules inside the process single meant square measure max-pooling, convolved muddled, data move, non-linearity, inclination move, snake tree, which is demonstrated in Fig.3.The convolves muddled implied as traditional line buffer, as demonstrated in Fig. 3, to acknowledge convolution operations on figure FC layer increase of matrix-vector
The consequence of arrangement will be in four potential cases, namely True Positive (TP), True Negative (TN), False Positive (FP), and False Negative (FN)

Summary

Research Article

To build the throughput of CNNs, equipment quickening agents utilizing General Processing Units (GPUs), Field Programmable Gate Array (FPGAs) and Application Specific Integrated circuits (ASICs) has been used. We offer rules to upgrade the utilization of FPGAs for the speeding up of CNNs. The proposed algorithm on to an FPGA platform and show that emotions recognition utterance duration 1.5s is identified in 1.75ms, while utilizing 75% of the resources. The proposed algorithm on to an FPGA platform and show that emotions recognition utterance duration 1.5s is identified in 1.75ms, while utilizing 75% of the resources This further demonstrates the suitability of our approach for real-time applications on Emotional Recognition system.

Introduction

Proposed Method

LAYERS USED TO BUILD CONVNETS

Converting FC Layers to CONV Layers

Findings

Conclusion