Urdhva Tiryakbhyam Research Articles

Comparative analysis of Vedic multiplier using Vedic sutras with existing multipliers in biomedical application

In today's computer world, a lot of real-time applications require rapid processing units. Arithmetic Logic Units (ALU) and Multiply-Accumulate (MAC) are the fundamental parts of these circuits and are necessary for their effective and rapid operation. The most significant prevalent part of digital signal processing devices is multipliers. The multiplier, adder, and registers need to be changed in order to maintain accuracy and increase execution speed, which will improve the performance of the ALU and MAC. The development of greater multipliers is being given priority for application in processors because of the increasing constraints on latency. To accelerate multiplication, it is essential to develop quicker multipliers. Vedic multipliers are preferred over different current expansions due to their low power consumption, fast operation, and efficient use of space. Vedic mathematics-based algorithms are often utilized to build quick, low-power multipliers. In addition to simulation results, this section covers the four sutras of Vedic mathematics: Urdhva Tiryakbhyam, Ekadhikena Purvena, Ekanyunena Purvena, and Nikhilam. Vedic multipliers are also compared to a variety of modern multipliers, including booth, Wallace, and array multipliers. All of the sutras are evaluated according to area, speed, power, propagation delay, and mean relative error (MRE) in the current research. The results of the study will be applied in the biomedical field.

FPGA Implementation of DFT Processor using Vedic Multiplier

Many a times Mathematical computations are easier in frequency domain than time domain. Discrete Fourier transform (DFT) is a tool to convert signals from time domain to frequency domain which is widely used mainly in Digital Signal and Image Processing applications. Fast Fourier Transform (FFT) is a method to find DFT in time constraint applications which is affected by number of complex multiplier. In this paper 16-bit DFT using Vedic Multiplier, a high- speed multiplier is proposed with an objective to replace conventional complex multiplier and to decrease computation time. The proposed system is implemented in Virtex-4 FPGA and the results show that FFT using Urdhva Tiryakbhyam algorithm of Vedic multiplier is faster than other methods of DFT

Optimized Multiplier Architectures for Enhanced Performance and Efficiency in MAC Units

This paper investigated the performance of Vedic multipliers in a 32-bit Multiplier-Accumulator Unit (MAC) by comparing Urdhva Tiryakbhyam and Nikhilam Sutras with various adder architectures. The goal was to identify the optimal combination of speed and resource efficiency. Urdhva Tiryakbhyam with CLA emerged as the fastest option, achieving a minimal delay of 0.709 ns. However, this came at the cost of higher resource utilization, measured in Logic Look-Up Tables (LUTs). Conversely, Nikhilam implementations generally required fewer LUTs, making them more resource-efficient, but they exhibited slightly slower performance. CLA consistently delivered the best delay for both Vedic multiplier types among the adder architectures. All the explored configurations are viable for practical implementation on Xilinx ISE 14.7. The key takeaway is that the choice between Urdhva Tiryakbhyam and Nikhilam and the specific adder architecture hinges on the application’s priorities.

An area efficient vedic multiplier for FFT processor implementation using 4-2 compressor adder

ABSTRACT This article proposes a compact compressor adder of Vedic multiplication for an area-efficient FFT architecture. A standard multi-radix-24,22,23 FFT with a single-path delay feedback structure is considered. Vedic multipliers employ the Urdhva Tiryakbhyam method, which reduces redundant steps and generates parallel partial products. The proposed 4–2 compressor adders have been introduced inside the vedic multiplier to minimize carry delay and speed up the multiplication process. The vedic multiplier designed on the compressor adder saves power and gate count. The devised FFT algorithm is implemented using 45nm CMOS technology. Simulation results show a gate reduction of 21.5% and power consumption of 18.5%. The throughput had increased to 1.86 GS/s at 186 MHz compared to existing FFT architectures.

Comparative Analysis of Vedic Multiplier using Various Adder Architectures

The performance of a microprocessor depends on the efficient multiplier as it is one of the most principal component in various digital circuits. This paper reviews optimization techniques for high speed Vedic multiplier design which is based on Urdhva Tiryakbhyam Sutra of Ancient Indian Vedic Mathematics. This particular sutra is the most efficient one as it gives minimum delay for all types of complex multiplication. Adder being the most important component in a multiplier design, using the efficient adder will enhance the performance of Vedic multiplier. During the comparison, different adder topologies like Carry Look ahead Adder, Kogge Stone Adder, Carry Skip Adder are used to compare area, delay and power. The reviewed methods are implemented on 45nanometer(nm), 90nm and 180 nm CMOS technology. The results of all the prior approaches are reviewed and an efficient method out of them has been proposed.

Comparison of Vedic Multiplier Implementation Using Gate Diffusion Input and Modified Gate Diffusion Input Techniques

Vedic maths is an ancient mathematical theory based on 16 sutras that has a unique computation technique. We employ the fourteenth sutra, 'Urdhva Tiryakbhyam', from the 16 sutras. Multiplication can be done 'vertically and crosswise' using this sutra. The creation of a high-speed Vedic Multiplier based on ancient Indian Vedic Mathematics principles that have been tweaked to boost efficiency. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. Multipliers are used in high-speed arithmetic logic units, multiplier and accumulate units, and other similar applications. With the rising limits on latency, the design of faster multiplications is becoming increasingly important. Many changes are being done to improve speed. Vedic multipliers based on Vedic Mathematics are among them. Power, area, and latency are the three fundamental restrictions in modern VLSI technological advancements. CMOS (Complementary metal-oxide-semiconductor) designs take up more space and use more energy. Power dissipation causes an IC to heat up, which has a direct impact on its reliability and performance. Gate Diffusion Input (GDI) technology reduces the size, propagation delay, and power consumption of digital circuits while also lowering logic complexity as compared to traditional CMOS and existing pass transistor logic approaches. We compared a 2x2 Vedic multiplier based on the GDI and mGDI (Modified GDI) techniques in this study. In comparison to the GDI approach, the mGDI technology employs much less transistors. The Vedic multiplier is implemented in the cadence virtuoso tool, on 180nm and 90nm technology.

A Review on IEEE-754 Standard Floating Point Multiplier using Vedic Mathematics

The fundamental and the core of all the Digital Signal Processors (DSPs) are its multipliers and the speed of the DSPs is mainly determined by the speed of its multiplier. IEEE floating point format is a standard format used in all processing elements since Binary floating point numbers multiplication is one of the basic functions used in digital signal processing (DSP) application. In this work VHDL implementation of Floating Point Multiplier using Vedic mathematics is carried out. The Urdhva Tiryakbhyam sutra (method) was selected for implementation since it is applicable to all cases of multiplication. Multiplication of two no’s using Urdhva Tiryakbhyam sutra is performed by vertically and crosswise. The feature is any multi-bit multiplication can be reduced down to single bit multiplication and addition using this method. On account of these formulas, the carry propagation from LSB to MSB is reduces due to one step generation of partial product.

Pipeline Architecture for N=K*2L Bit Modular ALU: Case study between current generation computing and Vedic computing

This paper describes a design architecture that performs mathematical operations using Vedic sutra for upward compatibility in pipeline manner. In spite of increasing the area, performance and reducing power, Vedic architecture have observed to be inherently compatible with higher efficiency for pipeline architecture. However Vedic architecture leads to additional flexibility starting from 2-bit base modules to 8-bit modules (L=1,2,3) and pipeline can be compactable to any base modules for any given length. Many researchers proposed arithmetic algorithms at simulation level using vedic sutra. These algorithm have been evaluated with better performance, area and speed. The literature has been widely found to be towards individual arithmetical operators like multiplier, square and cube and so on. A consolidated computing architecture, especially N-bit ALU is yet be realized Generalized N-bit ALU, can always be realized using pipeline modular architecture. The proposition is on realizing N-bit using ‘2L’ as base modules using ‘K’ modules in pipelining. The authors have extensively verified modular architecture for 4-Bit modules for 16 bit and 32 bit pipelined operations. Individually multiplication using Urdhva Tiryakbhyam, division using Dhwajanka sutra, square using Dwandwayoga sutra. MAC unit which involves multiplication algorithms used in FFT and IFFT using sutras of Vedic mathematics and it is possible to achieve reduce version interms of speed and delay, compared to different generations of ALU. The authors are now exploring N-bit ALU architecture FPGA implementation using Vedic sutras with flexible modular pipeline architecture and mainly targeted for Digital Signal processing applications.

Pipeline Architecture for N=K*2L Bit Modular ALU: Case study between current generation computing and Vedic computing

This paper describes a design architecture that performs mathematical operations using Vedic sutra for upward compatibility in pipeline manner. In spite of increasing the area, performance and reducing power, Vedic architecture have observed to be inherently compatible with higher efficiency for pipeline architecture. However Vedic architecture leads to additional flexibility starting from 2-bit base modules to 8-bit modules (L=1,2,3) and pipeline can be compactable to any base modules for any given length. Many researchers proposed arithmetic algorithms at simulation level using vedic sutra. These algorithm have been evaluated with better performance, area and speed. The literature has been widely found to be towards individual arithmetical operators like multiplier, square and cube and so on. A consolidated computing architecture, especially N-bit ALU is yet be realized Generalized N-bit ALU, can always be realized using pipeline modular architecture. The proposition is on realizing N-bit using ‘2L’ as base modules using ‘K’ modules in pipelining. The authors have extensively verified modular architecture for 4-Bit modules for 16 bit and 32 bit pipelined operations. Individually multiplication using Urdhva Tiryakbhyam, division using Dhwajanka sutra, square using Dwandwayoga sutra. MAC unit which involves multiplication algorithms used in FFT and IFFT using sutras of Vedic mathematics and it is possible to achieve reduce version interms of speed and delay, compared to different generations of ALU. The authors are now exploring N-bit ALU architecture FPGA implementation using Vedic sutras with flexible modular pipeline architecture and mainly targeted for Digital Signal processing applications.

Urdhva Tiryak Sutra Based Ancient Multiplication in Reversible Logic Circuits

The proposed work analyses the employment of an ancient mathematical approach for building an arithmetic logic unit. Dissipation of power is one of the major driving issues in VLSI design. With the assistance of reversible gates, the power dissipation and loss of information can be minimized. The speed and accuracy of the Arithmetic Logic Unit depends on the propagator. Employing the traditional mathematics sutras technique within the computation algorithm reduces the complexity, duration and power. Due to the effect of environmental factors on the digital circuits, parity conserving technique is incorporated for providing error detection ability. The proposed work deal with the design and analysis of 32 bit reversible multiplier using ancient sutras with and without parity conserving technique .The planned work is implemented on Xilinx ISE Spartan 6E series of FPGA and simulation results are obtained. By using Cadence EDA tool, power, area and delay are calculated. The quantum parameters are calculated manually for 32-bit reversible multiplier using ancient technique with and without parity conserving technique using Urdhva Tiryakbhyam sutra.

Implementation of high precision/low latency FP divider using Urdhva–Tiryakbhyam multiplier for SoC applications

The increasing demand of Industrial and Scientific data intensive applications are higher precision arithmetic with reduced computation time. In this paper, we designed a high-precision, fully pipelined 32-bit floating-point (FP) divider using Newton–Raphson (NR) algorithm realized with Urdhva–Tiryakbhyam (UT) multiplier for System on Chip applications. The divider design is based on Newton–Raphson (multiplicative) method and it supports all IEEE rounding modes with a latency of 15 cycles. The iterative NR computations are performed by using FP multiplier and FP adder. The key module of FP multiplier for calculating mantissa part is UT multiplier. It’s an ancient Vedic multiplication technique used from few centuries back for doing fast multiplications. We implemented two UT multipliers: one using carry look-ahead adders and another one using carry save adders. The results show that, the proposed architectures have 12% better precision with 24% high throughput than existing algorithms, at the cost of high on-chip power. The inputs to the divider are represented in IEEE-754 standard. The design uses Xilinx Vivado software and it is implemented on Virtex7 FPGA.

An Improved Area Efficient 16-QAM Transceiver Design using Vedic Multiplier for Wireless Applications

In this research article, an improved area efficient 16-Quadrature Amplitude Modulation (QAM) transceiver design is introduced using Vedic multiplier. The 16-QAM design is transmitted using Pseudo Random Binary Sequence (PRBS) and modulated by changeable clock frequencies. The Vedic multiplier uses Urdhva Tiryakbhyam (Vertical and Crosswise) method of multiplication to reduce the undesirable steps and generates parallel partial products. Compressor adders are used in the Vedic multipliers, which helps to increase the speed of multiplication process and reduces the carry delay. Four Compressor adders namely 5-3, 10-4, 15-4 and 20-5 are used in a 16-bit Urdhva Tiryakbhyam Vedic multiplier to add its partial products. The proposed 16-QAM design is implemented using Spartan-3 XC3S200-5 pq208 Field Programmable Gate Array (FPGA) device which occupies 672 slices, 1102 4-input Look up Tables (LUTs) and 39 mW of power consumption. The Vedic multiplier based 16-QAM transceiver design reduces 17.2% slices and 4.5% 4-input LUTs. The 16-QAM is a preferred digital modulation method in the Orthogonal Frequency Division Multiplexing (OFDM) system, which reduces bit errors and noise effects during data transmission. The OFDM transceiver design is used in the high-speed wireless communication by excellence of its Multi-carrier modulation method.

Delay Efficient Vedic Multiplier for DSP

Multipliers are very essential blocks in any arithmetic and logic unit, accumulators and Digital signal processors. Due to the enlarging check on delay, design of faster multipliers is desired. Amidst numerous multipliers, Vedic multipliers are favored for their speed of operation. There are sixteen sutras in Vedic mathematics out of which four are multiplication techniques. “URDHVA TIRYAKBHYAM” is the most efficient vedic multiplication technique in terms of speed. In this paper we aim to develop a multiplier using Ripple Carry Adder and parallel prefix adders which carry out the “URDHVA TIRYAKBHYAM” sutra with improved speed of operation by providing the minimum delay for the multiplication of numbers regardless of their bit sizes. A vast majority of the engineering domain consists of ubiquitous technologies like DSP. As it is one of the most rapid growing technologies of the 21st Century, it faces challenges and improvisation at each step. Engineers are working diligently to improve the quality of Digital Signal processors and major breakthroughs are being made at a very good rate. Proposed multiplier could be applied for such DSP applications. Verilog language has been used for the coding. Xilinx Vivado Tool is used for synthesis and Model Sim 5.4 has been used for simulation.

Complex Number Vedic Multiplier and its Implementation in a Filter

Complex numbers multiplication is a fundamental mathematical process in systems like digital signal processors (DSP). The main objective of complex number multiplication is to perform operations at lightning fast speed with less intake of power. In this paper, the best possible architecture is designed for a Real vedic multiplier based on the ancient Indian mathematical procedure known as URDHVA TIRYAKBHYAM SUTRA i.e. the structure of a MxM Vedic real multiplier architecture is developed. Then, a Vedic real multiplier solution of a complex multiplier is presented and its simulation results are obtained. The MxM Vedic real multiplier architecture, architecture of the Real Vedic multiplier solution for 32 x 32 bit complex numbers multiplication of complex multiplier and the architecture of a FIR filter has been code in Verilog and implementation is done through Modelsim 5.6 and Xilinx ISE 7.1 navigator.

Han–Carlson adder based high-speed Vedic multiplier for complex multiplication

Critical role is played by multipliers in modern digital signal processing systems. The overall system is affected by multipliers in terms of speed and computational complexity. In this paper, a Han–Carlson adder (HCA) based high-speed Vedic multiplier is proposed. The proposed Vedic multiplier uses Urdhva–Tiryakbhyam sutra of Vedic multiplication. Han–Carlson adder is one of the parallel-prefix adders which provides high-speed to the proposed multiplier architecture. Proposed architecture of 64 × 64 bit Vedic multiplier is implemented using Xilinx ISE 14.2 navigator in VHDL. The implementation results of proposed architecture are compared with conventional Vedic multipliers with different adders which show that the conventional multipliers is having larger time delay as compared to proposed multiplier. Furthermore, complex multiplication architectures, using three and four 32 × 32 bit proposed Vedic multipliers are also implemented. The results of these complex multiplication architectures are also compared with conventional Booth multiplier and Array multiplier based architectures which show that the complex multiplication using proposed architecture provides improved delay, low hardware (LUTs) and low complexity.

A Delay Efficient Vedic Multiplier

Vedic mathematics is the ancient Indian method of mathematics based on 16 Sutras applicable to various branches of mathematics like trigonometry, calculus, geometry, conics etc. Multiplication is effectively used in modern communication and Digital Signal Processing applications. Ordinary multiplication requires propagation of carry from LSB to MSB while adding binary partial products, which limits the overall speed of multiplication. Vedic mathematics helps in generation of partial products and sums in one step, and ensures reduction in overall propagation delay. Urdhva Tiryakbhyam Sutra and Nikhilam Sutra are the two multiplication techniques used in Vedic mathematics. In this paper, an 8 * 8 Nikhilam Sutra multiplier for three different sets of bases is realized. The concepts of Urdhva Tiryakbhyam Sutra multiplication are used for the implementation of the proposed multiplier. The implementation results are compared with that of a Modified Booth’s multiplier in terms of delay, area and power. The design is synthesized in Synopsys Design Compiler using CMOS 90 nm technology, and results show that the proposed multiplier using Nikhilam Sutra with 25 bases is faster than the Modified Booth’s multiplier by 51.28%.

Design and Implementation of High Speed Vedic Multiplier in SPARTAN 3 FPGA Device

Digital systems which are more effective are necessary due to the enormous growth in the technology. So, we go for multipliers which are playing a key role in each and every digital domain device. Also, designing a multiplier with high speeds to perform ALU operations is an important aspect in digital signal processing. These operations are used for DFT, convolution etc. Hence, professionals in DSP domain are trying to develop innovative algorithms and hardware implementation. It is very essential to employ a multiplier which is more effective. They are many standard algorithms that are existing to reduce the area and time needed for execution. Vedic era described algorithms in vedic mathematics that supply an efficiency which are of high level. They provide 16 sutras for the operation of multiplication. Here, we discuss about urdhva tiryakbhyam algorithm for multiplication operation. Therefore, vedic algoritm provides better efficiency in comparison to that of conventional multipliers.

VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

Background: Since multiplication dominates the execution time of most DSP algorithms, there is a need of high speed, area efficient and power efficient multiplier. Also, many patents emphasize on the fact that multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip. Hence, there is a need for high speed- low power multipliers. This can be achieved by using the concept of Vedic Mathematics as multipliers based on Vedic Mathematics is one of the fast and low power multiplier Urdhva tiryakbhyam, Nikhilam, sutras forms the basic Vedic formulas in the design of Vedic multipliers. Keywords: Vedic sutra, karatsuba algorithm, DFT, array multiplier, radix-4 technique, urdhva tryagbhyam sutra.

Implementation of Delay Efficient ALU using Vedic Multiplier with AHL

Digital multipliers are most widely used component in applications such as convolution, Fourier transform, discrete cosine transforms, and digital filtering. Because outturn of these applications mainly depends on multiplier speed, therefore multipliers must be designed efficiently. In the proposed architecture, a variable-latency multiplier design with novel AHL architecture and a razor flip flop is used, which results in reduced delay and increased speed than the existing system. Meanwhile proposed architecture is used to compare array multiplier, column-bypassing multiplier, rowbypassing multiplier and Vedic multiplier. The experimental result shows that the Vedic multiplier has better performance in power consumption and delay. Here in this work Vedic multiplication is done using Urdhva Tiryakbhyam Sutra (Algorithm), which results in minimum delay. Thus using Vedic multiplier ALU is designed which results in enhanced performance compared to contemporary design.

Implementation for Minimization of Computation Time of Partial Products for Designing Multipliers using Tabulated Vedic Mathematics

Multiplication is the most time consuming process in various signal processing operations like Convolution, Circular Convolution, auto-correlation, and Cross Correlation, Image processing applications such as edge detection, microprocessors arithmetic and logical units etc. The multiplier circuit uses adder logic which reduces speed of operation due to its path propagation delay. The designs used offer tradeoffs between Computational time area, latency and throughput for performing multiplication. In this paper an ancient Indian Vedic mathematics sutras base multiplier have been proposed with Urdhva Tiryakbhyam sutra. In this methodology the length of input sequence used for multiplication varies from two to eight.