Abstract
Complex numbers multiplication is a fundamental mathematical process in systems like digital signal processors (DSP). The main objective of complex number multiplication is to perform operations at lightning fast speed with less intake of power. In this paper, the best possible architecture is designed for a Real vedic multiplier based on the ancient Indian mathematical procedure known as URDHVA TIRYAKBHYAM SUTRA i.e. the structure of a MxM Vedic real multiplier architecture is developed. Then, a Vedic real multiplier solution of a complex multiplier is presented and its simulation results are obtained. The MxM Vedic real multiplier architecture, architecture of the Real Vedic multiplier solution for 32 x 32 bit complex numbers multiplication of complex multiplier and the architecture of a FIR filter has been code in Verilog and implementation is done through Modelsim 5.6 and Xilinx ISE 7.1 navigator.
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