VLSI Implementation of High Speed-Low Power-Area Efficient Multiplier Using Modified Vedic Mathematical Techniques

Abstract

Background: Since multiplication dominates the execution time of most DSP algorithms, there is a need of high speed, area efficient and power efficient multiplier. Also, many patents emphasize on the fact that multiplication time is still the dominant factor in determining the instruction cycle time of a DSP chip. Hence, there is a need for high speed- low power multipliers. This can be achieved by using the concept of Vedic Mathematics as multipliers based on Vedic Mathematics is one of the fast and low power multiplier Urdhva tiryakbhyam, Nikhilam, sutras forms the basic Vedic formulas in the design of Vedic multipliers. Keywords: Vedic sutra, karatsuba algorithm, DFT, array multiplier, radix-4 technique, urdhva tryagbhyam sutra.